
MJ-D707, MJ-17D
49
No.
Name
Description
1
DQ1
Data Input/Output
2
DQ2
3
W
Write control input
4
RAS
Line address strobe input
5
A9
Address input
6
|
8
9
A0
|
|
Address input
12
A3
13
Vcc
Power supply voltage (+3.3 V)
13
12
11
10
9
5
4
3
2
1
DQ1
DQ2
W
RAS
A9
A0
A1
A2
A3
VCC
VSS
DQ4
DQ3
CAS
OE
A8
A7
A6
A5
A4
14
15
16
17
18
22
23
24
25
26
4
3
10
23
14
15
12
11
16
17
18
Clock Generation Circuit
Memory Cell
(4194304bits)
Sense Reflesh Amp.
Input/Output
Control Circuit
Address Buffer
Line Decoder
Column Decoder
Output
Buffer
Input
Buffer
A0
A1
A2
A3
A4
A5
A6
A7
A8
9
24
DQ2
DQ3
25
DQ4
13
Vcc (3.3V)
26
Vss (0V)
22
2
DQ1
1
A9
5
CAS
RAS
W
OE
7. GENERAL INFORMATION
7.1.1 IC
7.1 PARTS
Block Diagram
Pin Function
M5M4V4400CTP-7 (IC103: CORE MAIN UNIT ASSY)
DRAM
Pin Assignment (Top view)
¶
The information shown in the list is basic information and may
not correspond exactly to that shown in the schematic diagrams.
No.
Name
Description
14
A4
|
|
Address input
18
A8
19
|
21
22
OE
Output-enable input
23
CAS
Column address strobe input
24
DQ3
Data Input/Output
25
DQ4
26
Vss
Ground (0 V)