104
DV-AX10
• The information shown in the list is basic information and may not correspond exactly to that shown in the schematic diagrams.
BU2185F (DVDM ASSY : IC959)
• Clock Generate IC
•
Block Diagram
7.2 PARTS
7.2.1 IC
•
List of IC
BU2185F, LC89055W-RA8, PD3410A, PM0024AF, CY2071ASL-371
•
Pin Function
•
Truth Table
1
2
11
9
14
XTAL1IN
XTAL1OUT
15
3
CTRL1
CTRL2
CLK2
(27.0000MHz)
CLK1
(36.8640MHz)
(18.4320MHz)
CLK3
(33.8688MHz)
XTAL1
OSC
PLL1
DATA1A
DATA1B
1/2
H
SW
L
PLL2
7
8
XTAL2IN
XTAL2OUT
16
OE
XTAL2
OSC
CTRL1 CTRL2 SW
PLL1
PLL2
H
L
H
DATA1A DATA2A
L
L
L
DATA1A DATA2A
H
H
H
DATA1B DATA2B
L
H
L
DATA1B DATA2B
No. Pin Name
Function
1
XTAL1-IN
Reference OSC input 1 (Not used)
2
XTAL1-OUT
Reference OSC output 1
3
CTRL2
X'tal setting L: 36.8M mode, H: 18.4M mode
4
AGND
Analog GND
5
DGND
Digital GND
6
DVDD
Independent power supply for XTAL2-IN and
XTAL2-OUT
7
XTAL2-IN
Reference OSC input 2
(36.864MHz or 18.432MHz)
8
XTAL2-OUT
Reference OSC output 2
9
CLK1
Reference clock output
(36.864MHz or 18.432MHz)
10
DVDD
Independent power supply for CLK1
output buffer
11
CLK2
Clock output 2 (27.000MHz)
12
DVDD
Digital VDD
13
AVDD
Analog VDD
14
CLK3
Clock output 3 (33.8688MHz)
15
CTRL1
CLK1 output select
H: 36.864MHz, L: 18.432MHz
16
OE
Output enable H: enable, L: disable
DATA1A=XTAL2
×
375/128/4
DATA1B=XTAL2
×
375/64/4
DATA2A=XTAL2
×
147/40/4
DATA2B=XTAL2
×
147/20/4
DATA2A
DATA2B
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