46
DJM-850-K
1
2
3
4
A
B
C
D
E
F
1
2
3
4
• Pin Function
51
A
V
SS
G
G
N
DD_REFB_PA
Reference ground for AD/DA
−
52
P157/A
N
I15
I
V
R_I
N
1
V
R IC 1_1 (for IC6604)
−
53
P156/A
N
I14
I
V
R_I
N
2
V
R IC 1_2 (for IC6604)
−
54
P155/A
N
I13
I
V
R_I
N
3
V
R IC 2_1 (for IC6603)
−
55
P154/A
N
I12
I
V
R_I
N
4
V
R IC 2_2 (for IC6603)
−
56
P153/A
N
I11
I
V
R_I
N
5
V
R IC 3_1 (for IC6602)
−
57
P152/A
N
I10
I
V
R_I
N
6
V
R IC 3_2 (for IC6602)
−
5
8
P151/A
N
I9
I
EFX_CH_SEL
Effect CH select (Perform a voltage value in AD)
−
59
P150/A
N
I
8
O
SUB_I
N
T
Interrupt request signal to MAI
N
UCOM
−
60
P27/A
N
I7
I
KEY_I
N
7
Key input signal 7
−
61
P26/A
N
I6
I
KEY_I
N
6
Key input signal 6
−
62
P25/A
N
I5
I
KEY_I
N
5
Key input signal 5
−
63
P24/A
N
I4
I
KEY_I
N
4
Key input signal 4
−
64
P23/A
N
I3
I
KEY_I
N
3
Key input signal 3
−
65
P22/A
N
I2
I
KEY_I
N
2
Key input signal 2
−
66
P21/A
N
I1
I
KEY_I
N
1
Key input signal 1
−
67
P20/A
N
I0
I
KEY_I
N
0
Key input signal 0
−
6
8
P130
O
N
C
N
ot used (open)
×
69
P131/TI06/TO06
I
CFX1_S
W
CFX_S
W
1 key input
×
70
P04/SCK10/SCL10
I
CFX2_S
W
CFX_S
W
2 key input
×
71
P03/SI10/RxD1/SDA10
O
N
C
N
ot used (open)
×
72
P02/SO10/TxD1
O
N
C
N
ot used (open)
×
73
P01/TO00
O
V
R_SEL_1_0
V
R select (1_0, 1_1) for IC6603, 6604
×
74
P00/TI00
O
V
R_SEL_1_1
×
75
P145/TI07/TO07
O
FL_BK
Break signal for FL
×
76
P144/SO20/TxD2
O
FL_TXD
Sync serial data output for FL update
×
77
P143/SI20/RxD2/SDA20
I
TAP_S
W
1
TAP S
W
key input
×
7
8
P142/SCK20/SCL20
O
FL_SCK
Serial clock output for FL update
×
79
P141/PCLBUZ1/I
N
TP7
I
CFX3_S
W
CFX_S
W
3 key input
×
8
0
P140/PCLBUZ0/I
N
TP6
I
CFX4_S
W
CFX_S
W
4 key input
×
8
1
P120/I
N
TP0/EXL
V
I
O
FPGA_SIG
N
AL
Communication start signal to FPGA
×
8
2
P47/I
N
TP2
O
N
C
N
ot used (open)
×
8
3
P46/I
N
TP1/TI05/TO05
O
FL_LAT
Latch signal for FL
×
8
4
P45/SO01
O
FPGA_TX_DAT
Transmit data of FPGA
×
8
5
P44/SI01
I
FPGA_RX_DAT
Receive data from FPGA
×
8
6
P43/SCK01
O
FPGA_CLK
Data transmission and reception clock with FPGA
×
8
7
P42/TI04/TO04
I
SUB_CTRL
SUB UCOM control signal (Communication permission signal from MAI
N
UCOM)
×
88
P41/TOOL1
O
TOOL1
Clock output for debugger
×
8
9
P40/TOOL0
O
TOOL0
Flash memory programmer/Clock input, output for debugger
×
90
RESET
I
SUB_CPU_RESET
Reset cancellation from MAI
N
UCOM
−
91
P124/XT2
I
E
N
C1_1
Encoder 1
−
92
P123/XT1
I
E
N
C1_0
Encoder 1
−
93
FLMD0
I
FLMD0
Draw a flash memory programming mode
−
94
P122/X2/EXCLK
O
X2
X1 (crystal/ceramic) oscillation
−
95
P121/X1
I
X1
X1 (crystal/ceramic) oscillation
−
96
REGC
V
REGC
Regulator output for internal working, be connected to
V
ss through a capacitor.
−
97
V
SS
G
G
N
DD
Ground
−
9
8
E
V
SS0
G
G
N
DD
Ground for port
−
99
V
DD
V
V
+3R3D_PA
Power supply
−
100
E
V
DD0
V
V
+3R3D_PA
Power supply for port
−
N
ote "
−
": There is no built-in pulling up function
No.
I/O Port Name
I/O
Signal Name
Description
Pull-up
(Note)
Содержание DJM-850-K
Страница 9: ...9 DJM 850 K 5 6 7 8 5 6 7 8 A B C D E F ...
Страница 17: ...17 DJM 850 K 5 6 7 8 5 6 7 8 A B C D E F ...