44
DJM-850-K
1
2
3
4
A
B
C
D
E
F
1
2
3
4
• Pin Function
51
A
V
SS
G
G
N
DREF_A
Ground
−
52
P157/A
N
I15
I
V
R_TRIM4
Trim 4
−
53
P156/A
N
I14
I
V
R_FADER4
CH4 fader
−
54
P155/A
N
I13
I
V
R_TRIM3
Trim 3
−
55
P154/A
N
I12
I
V
R_TRIM2
Trim 2
−
56
P153/A
N
I11
I
V
R_FADER3
CH3 fader
−
57
P152/A
N
I10
I
V
R_TRIM1
Trim 1
−
5
8
P151/A
N
I9
I
V
R_FADER_CRS
Cross fader
−
59
P150/A
N
I
8
I
V
R_FADER2
CH2 fader
−
60
P27/A
N
I7
I
V
R_FADER1
CH1 fader
−
61
P26/A
N
I6
O
N
C
N
ot used (open)
−
62
P25/A
N
I5
O
DSP_RESET
DSP reset
−
63
P24/A
N
I4
O
DIT_RESET
DIT reset
−
64
P23/A
N
I3
O
DOUT_SRC_RESET
DIT SRC reset
−
65
P22/A
N
I2
O
AD_DA_RESET
ADC DAC reset
−
66
P21/A
N
I1
O
N
C
N
ot used (open)
−
67
P20/A
N
I0
O
DBG_PORT2(
N
C)
Palpation port for microcomputer debug
−
6
8
P130
O
STBY_LED
UTILITY/Standby cancellation key indicator
×
69
P131/TI06/TO06
O
DSP_USB_
W
P
W
rite protect (4 MBit serial FLASH for MAI
N
, DSP common use)
×
70
P04/SCK10/SCL10
O
MFL_SCK
Sync serial clock output for MAI
N
Flash
×
71
P03/SI10/RxD1/SDA10
I
MFL_RxD
Sync serial data input for MAI
N
Flash
×
72
P02/SO10/TxD1
O
MFL_TxD
Sync serial data output for MAI
N
Flash
×
73
P01/TO00
O
MFL_CS
Chip select for MAI
N
Flash
×
74
P00/TI00
I
EFX_O
N
/OFF
Beat effect O
N
/OFF switch
×
75
P145/TI07/TO07
O
MFL_
W
P
W
rite protect (4 MBit serial FLASH for built-in MAI
N
)
×
76
P144/SO20/TxD2
O
MIDI_TXD
MIDI output
×
77
P143/SI20/RxD2/SDA20
O
FPGA_RESET
FPGA reset
×
7
8
P142/SCK20/SCL20
O
FPGA_XPGM
PROG_B output signal
×
79
P141/PCLBUZ1/I
N
TP7
I
SUB_I
N
T
N
otice during the access to FPGA and external interrupt
generation signal to SUB UCOM
×
8
0
P140/PCLBUZ0/I
N
TP6
I
STBY_KEY
Standby cancel interrupt, external interrupt pin
×
8
1
P120/I
N
TP0/EXL
V
I
O
DBG_PORT1(
N
C)
Palpation port for microcomputer debug
×
8
2
P47/I
N
TP2
O
DBG_PORT0(
N
C)
Palpation port for microcomputer debug
×
8
3
P46/I
N
TP1/TI05/TO05
O
DSP_USB_CS
Chip select for DSP Update/USB Boot (course switch)
×
8
4
P45/SO01
O
DSP_USB_SO
Serial data output for DSP Update/USB Boot
×
8
5
P44/SI01
I
DSP_USB_SI
Serial data input for DSP Update/USB Boot
×
8
6
P43/SCK01
O
DSP_USB_CLK
Serial clock output for DSP Update/USB Boot
×
8
7
P42/TI04/TO04
I
RETER
N
_I
N
RETUR
N
output connection confirmation switch
×
88
P41/TOOL1
O
TOOL1
Clock output for debugger
×
8
9
P40/TOOL0
I/O
TOOL0
Flash memory programer/Data input, output for debugger
×
90
RESET
I
RESET_OUT
Reset cancellation of MAI
N
UCOM
−
91
P124/XT2
I
FPGA XI
N
IT
I
N
T_B input signal
−
92
P123/XT1
I
FPGA_DO
N
E
DO
N
E input signal (for end judgments)
−
93
FLMD0
I
FLMD0
Draw a flash memory programming mode
−
94
P122/X2/EXCLK
O
X2
X2 (crystal/ceramic) oscillation
−
95
P121/X1
I
X1
X2 (crystal/ceramic) oscillation
−
96
REGC
O
REGC
Regulator output for internal working
−
97
V
SS
G
G
N
DD
Ground
−
9
8
E
V
SS0
G
G
N
DD
Ground
−
99
V
DD
V
V
+3R3E
Power supply (Connect to 3.3
V
)
−
100
E
V
DD0
V
V
+3R3E
Power supply (Connect to 3.3
V
)
−
N
ote "
−
": There is no built-in pulling up function
No.
I/O Port Name
I/O
Signal Name
Description
Pull-up
(Note)
Содержание DJM-850-K
Страница 9: ...9 DJM 850 K 5 6 7 8 5 6 7 8 A B C D E F ...
Страница 17: ...17 DJM 850 K 5 6 7 8 5 6 7 8 A B C D E F ...