DJM-800
157
5
6
7
8
5
6
7
8
C
D
F
A
B
E
No.
Pin Name
I/O
IPD/IPU
Pin Function
97
VSS
−
−
GND
98
DVDD
−
−
Power supply
99
EA17
O
IPU
For SD-RAM access (address) External address
100
EA19
O
IPU
For SD-RAM access (address) External address
101
EA20
O
IPU
For SD-RAM access (address) Vacant (FREE)
102
xCE0
O
IPU
For SD-RAM access (signal) DPRAM (FPGA) ACCESS
103
xCE1
O
IPU
For SD-RAM access (signal) FLASH ROM ACCESS
104
CVDD
−
−
Power supply
105
CVDD
−
−
Power supply
106
VSS
−
−
GND
107
DVDD
−
−
Power supply
108
xBE1
−
IPU
For SD-RAM access (signal) xBE1
109
EA21
O
IPU
For SD-RAM access (address) Vacant (FREE)
110
xBE0
−
IPU
For SD-RAM access (signal) xBE0
111
ED13/GP1[13]
I/O
IPU
For SD-RAM access (data) External data bus
112
ED15/GP1[15]
I/O
IPU
For SD-RAM access (data) External data bus
113
ED14/GP1[14]
I/O
IPU
For SD-RAM access (data) External data bus
114
DVDD
−
−
Power supply
115
VSS
−
−
GND
116
CVDD
−
−
Power supply
117
ED11/GP1[11]
I/O
IPU
For SD-RAM access (data) External data bus
118
ED12/GP1[12]
I/O
IPU
For SD-RAM access (data) External data bus
119
ED9/GP1[9]
I/O
IPU
For SD-RAM access (data) External data bus
120
ED10/GP1[10]
I/O
IPU
For SD-RAM access (data) External data bus
121
ED6/GP1[6]
I/O
IPU
For SD-RAM access (data) External data bus
122
ED7/GP1[7]
I/O
IPU
For SD-RAM access (data) External data bus
123
ED8/GP1[8]
I/O
IPU
For SD-RAM access (data) External data bus
124
CVDD
−
−
Power supply
125
VSS
−
−
GND
126
DVDD
−
−
Power supply
127
ED4/GP1[4]
I/O
IPU
For SD-RAM access (data) External data bus
128
ED5/GP1[5]
I/O
IPU
For SD-RAM access (data) External data bus
129
ED3/GP1[3]
I/O
IPU
For SD-RAM access (data) External data bus
130
ED2/GP1[2]
I/O
IPU
For SD-RAM access (data) External data bus
131
ED1/GP1[1]
I/O
IPU
For SD-RAM access (data) External data bus
132
ED0/GP1[0]
I/O
IPU
For SD-RAM access (data) External data bus
133
CVDD
−
−
Power supply
134
VSS
−
−
GND
135
xHINT/GP0[1]
−
IPU
Open(FREE)
136
BUSREQ
−
IPU
For SD-RAM access (signal) Vacant (FREE)
137
xHOLDA
−
IPU
For SD-RAM access (signal) Vacant (FREE)
138
xHOLD
−
IPU
For SD-RAM access (signal) Set to "H".
139
HHWIL/AFSR1
I
IPU
McASP1 McASP receive LRCLK(FS)
140
xHRDY/ACLKR1
I
IPD
McASP1 McASP receive bit clock
141
DVDD
−
−
Power supply
142
VSS
−
−
GND
143
HR/W/AXR0[15]/AXR1[0]
I
IPU
McASP1 CH1 IN
144
HCNTL1/AXR0[14]/AXR1[1]
I
IPU
McASP1 CH2 IN
IPD = Internal pulldown, IPU = Internal pullup.
Содержание DJM-800
Страница 35: ...DJM 800 35 5 6 7 8 5 6 7 8 C D F A B E 1 3 CN6 I CN1503 B ...
Страница 38: ...DJM 800 38 1 2 3 4 1 2 3 4 C D F A B E 3 14 PANEL 2 ASSY CN1710 C CN1711 C PANEL2 ASSY DWX2554 F F ...
Страница 39: ...DJM 800 39 5 6 7 8 5 6 7 8 C D F A B E Holder MASTER VOL LEVEL ZERO DETECTOR F ...
Страница 47: ...DJM 800 47 5 6 7 8 5 6 7 8 C D F A B E 3 3 I 3 3 I 3 3 I 1 3 I 1 3 2 3 I ...
Страница 49: ...DJM 800 49 5 6 7 8 5 6 7 8 C D F A B E HPD SDD BOD MA1D MA2D RECD 1 2 5 3 4 1 3 I 1 3 I 3 3 I 3 3 I 1 3 2 3 I ...
Страница 53: ...DJM 800 53 5 6 7 8 5 6 7 8 C D F A B E 1 3 I 1 3 I 1 3 I 1 3 I 2 3 I 1 3 I 1 3 2 3 I ...
Страница 63: ...DJM 800 63 5 6 7 8 5 6 7 8 C D F A B E D3 D4 D3 D4 D4 D4 D3 D3 CN1401 L ...
Страница 64: ...DJM 800 64 1 2 3 4 1 2 3 4 C D F A B E 3 24 DIGIB ASSY BUFFER D D D MA2D D 2 4 3 DIGIB ASSY DWX2546 M M ...
Страница 71: ...DJM 800 71 5 6 7 8 5 6 7 8 C D F A B E Q CN 8 I 2 3 CN 2502 O CN903 J ...