Pilz PMCtendo DD5, Руководство по эксплуатации

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EtherCAT
Operating Manual EtherCAT for, PMCtendo DD5 and PMCprotego D
1002906-EN-02
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4.2 AL event (interrupt event) and interrupt enable
The communication between the drive and EtherCAT FPGA is completely interrupt-con-
trolled. The Interrupt enable register and the Al event register are responsible for the inter-
rupt functionality of the EtherCAT interface. With a 1 in the corresponding Bit of the Inter-
rupt enable register the servo amplifier activates the individual events of the EtherCAT in-
terface, with a 0 the events are deactivated.
4.2.1 Interrupt enable register (address 0x0204:0205)
Parameter Address Bit
ZA
Drive
ZA
ECAT Description
AL Control
Event
0x204 0 r/w r Activating the AL Control
Events for phase runup
-- 0x204 1 r/w r Reserved
DC Distributed
Clock
0x204 2 r/w r Activating the Distributed Clock
(DC) Interrupts for the complete
communication
-- 0x204 3 … 7 r/w r Reserved
Mail Out Event 0x205 0 r/w r Activating the Mailbox Output
Event (SDO, Sync Manager 0)
for the object channel
Mail In Event 0x205 1 r/w r Activating the Mailbox Input
Event (SDO, Sync Manager 1)
for the object channel
Pro Out Event 0x205 2 r/w r Activating the process data
Output Event (PDO, cyclical set
values of the card)
Pro In Event 0x205 3 r/w r Activating the process data In-
put Event (PDO, cyclical actual
values of the servo amplifier)
-- 0x205 4 … 7 r/w r Reserved
With a 1 in the relevant Bit of the AL Event register the EtherCAT interfaces signals to the
servo amplifier in the Interrupt routine which event is to be processes by the servo amplifier.
4.2.2 AL Event (address 0x220:0221)
Parameter Address Bit
ZA
Drive
ZA
ECAT Description
AL Control Event 0x220 0 r r/w Editing the AL Control Events for
phase runup
Sync Manager
Watchdog Event
0x220 1 r r/w Editing a Sync Manager Watch-
dog Event
Distributed Clock
(DC) Event
0x220 2 r r/w Editing a Distributed Clock (DC)
Event
-- 0x220 3 … 7 r r/w Reserved