PCM-065/phyCORE-i.MX8X System on Module
L-864e.A1
© PHYTEC America LLC, 2021
44
PHY Address
0
Mirror Mode
Enabled
Auto-negotiation
Enabled (advertise ability of 10/100/1000)
RGMII TX Clock Skew
1.5 ns
RGMII RX Clock Skew
1.5 ns
6.3
I
2
C
The Inter-Integrated Circuit (I
2
C) interface is a two-wire, bidirectional serial bus that provides a simple and
efficient method for data exchange among devices. The phyCORE-i.MX8X SOM provides ten independent
multimaster fast-mode I
2
C modules, though the PMIC_I2C is not accessible from the phyCORE-Connector as it
is dedicated to the PMIC and M40_I2C is dedicated to the Cortex M4F. For eight of the I2Cs there are two types
of I2C: High-speed I2C ports with DMA support (I2C0, I2C1, I2C2, and I2C3) and low-speed I2C ports with no
DMA support (MIPI-DSI0-I2C, MIPI-DSI1-I2C0, MIPI-CSI0-I2C0, and CSI I2C) which are used in conjunction
with a specific PHY interface. I2C ports associated with a PHY (e.g. MIPI DSI) can be used generally but require
the PHY to be powered on even if the PHY interface itself is not used.
Table 22. Connections at the phyCORE-Connector
X1 Pin #
Processor Signal
SOM Signal
Type
Level
Processor
Ball
Description
C12
MIPI-DSI0-I2C0-SCL
X_MIPI_DSI0_I2C0_SCL
OD-O
3.3V
W27
MIPI DSI0 I2C0 Clock
C11
MIPI-DSI0-I2C0-SDA
X_MIPI_DSI0_I2C0_SDA
OD-I/O
3.3V
V22
MIPI DSI0 I2C0 Data
C41
MIPI-DSI1-I2C0-SCL
X_MIPI_DSI1_I2C0_SCL
OD-O
3.3V
AE33
MIPI DSI1 I2C0 Clock
C42
MIPI-DSI1-I2C0-SDA
X_MIPI_DSI1_I2C0_SDA
OD-I/O
3.3V
AC29
MIPI DSI1 I2C0 Data
D36
MIPI-CSI0-I2C0-SCL
X_MIPI_CSI0_I2C0_SCL
OD-O
1.8V
AP26
MIPI CSI0 I2C0 Clock
D37
MIPI-CSI0-I2C0-SDA
X_MIPI_CSI0_I2C0_SDA
OD-I/O
1.8V
AM24
MIPI CSI0 I2C0 Data
D33
I2C0_SCL
X_MIPI_CSI0_GPIO0_00 OD-O
1.8V
AR25
Main I2C0 Clock
D34
I2C0_SDA
X_MIPI_CSI0_GPIO0_01 OD-I/O
1.8V
AP24
Main I2C0 Data
B8
I2C1_SCL
X_USB3_SS3_TC1
OD-O
3.3V
H14
Main I2C1 Clock
B11
I2C1_SDA
X_USB3_SS3_TC3
OD-I/O
3.3V
C15
Main I2C1 Data
C43
I2C2_SCL
X_MIPI_DSI1_GPIO0_00 OD-O
3.3V
AD30
Main I2C2 Clock
C44
I2C2_SDA
X_MIPI_DSI1_GPIO0_01 OD-I/O
3.3V
AF34
Main I2C2 Data
B56
I2C3_SCL
X_SPI3_CS1
OD-O
3.3V
F28
Main I2C3 Clock
A54
I2C3_SDA
X_MCLK_IN1
OD-I/O
3.3V
M22
Main I2C3 Data
D59
M40 I2C_SCL
X_ADC_IN0
OD-O
1.8V
U35
M40 I2C Clock
D58
M40 I2C_SDA
X_ADC_IN1
OD-I/O
1.8V
U33
M40 I2C Data
D26
CSI I2C_SCL
X_CSI_EN
OD-O
3.3V
AP28
CSI I2C Clock
D27
CSI I2C_SDA
X_CSI_RESET
OD-I/O
3.3V
AR27
CSI I2C Data
6.4
Media Local Bus
The phyCORE-i.MX8X SOM provides a Media Local Bus interface that provides a link to a MOST® data network,
using the standardized MediaLB protocol. It supports a 3-wire interface (MLB25,MLB50).
