Circuit Descriptions
7.
Figure 7-20 TCON architecture
For the TCON block diagram, refer to figure
.
Figure 7-21 TCON block diagram
1
8
770_2
38
_100127.ep
s
100402
EEPROM
TFT – LCD Panel
Mini - LVD
S
Control
S
i
g
nal
s
+
3
.
3
V
+1.
8
V
V
GH
(+2
8
V)
V
GL
(-6 V)
+12 V
LVD
S
(10 bit)
Timin
g
Controller
Power
Block
Gamma
Reference
Volta
g
e
S
ource Drive IC
Gate Drive IC
PNX
8
550
LC D P anel
T C O N
M ain P latform
S S
B
+16 V
(TCON)
1
8
770_2
3
9_100127.ep
s
100127
LV D
S
R e c e iv er
LV D
S
R e c e iv er
Ve rtic a l & H o rizo n ta l
Tim in
g
g
e n e ra tio n
D a ta
P a th
B lo c k
(L in e
B u ffer)
M ini-LVD
S
Tran
s
mitter
M ini-LVD
S
Tran
s
mitter
O P C
(Optimum
Power
Control)
(Over
Drive
Circuit)
(Dynamic
Contra
s
t
Control)
O D C D C A
F
o
rm
a
tt
e
r/
S
er
ia
li
z
e
r
S
p re a d
S
p e c tru m
S
D R A M
I
2
C
S
lav e
I
2
C
M a
s
ter
R O M
E E P R O M
1 6 bit
H
s
y n c
/
V
s
ync
DE
S S
C L K
(
S
p re a d
S
pectrum C lo c k)
RLV P /N
Ri
g
ht h alf
data
Gate D river
C trl
S
i
g
n al
s
S
ource D river
C trl
S
i
g
n al
s
R 1 A ~E
R 1 C L K
R 2 C L K
R 2 A ~E
M in i-
LVD
S
Output
LVD
S
Input
Control
S
i
g
nal
Output
T im in
g
C o n tro lle r IC