MG5.1E
11. Digital convergence circuit
83
Personal notes
Figure 11-4
3007
6002
3019
330R
330R
3092
6K8
3093
3K3
3094
3K3
3101
1K
3102
47R
7012
2042
220n
8V6
8V6
330R
3008
330R
3020
6003
2041
47R
1K
3096
3K3
3097
6K8
3095
220n
3K3
7013
8V6
3103
8V6
3104
3009
330R
3021
330R
6004
3100
3K3
8V6
3098
6K8
220n
2040
3099
3K3
7014
1K
3105
47R
3106
8V6
+5V2
7005
3006
220R
3005
4K7
3004
2K2
3003
2K2
6020
1377-1
INT
1377-4
CONV_BL
1377-6
CONV-GRN
1377-8
CONV_RED
FROM CONVERGENCE
PANEL
1364-4
BLUE
1364-3
GREEN
1364-1
RED
TO SMALL
SIGNAL PANEL
6019
6018
3107
150R
3108
150R
1377-2
LRB
FB
1364-2
LRB
CL 96532100_105.eps
151199
During the Convergence adjustment mode, the Blue, Green,
and Red cross hatch pattern signals are fed to the Interface
panel on connector 1370, Pins 4, 6, and 8. (Figure 11-4) Fast
blanking (LRB) is fed to the panel on connector 1370, Pin 2. An
intensity control from the Convergence microprocessor is fed to
transistor 7005 on the Interface panel. This sets the bias level
of the three buffer transistors 7012, 7013, and 7014 to control
the intensity of the convergence pattern. The output of the three
buffer transistors is then fed to the Video Processing section of
the Small Signal panel. The Icon used for the convergence
adjustment is generated on the Small Signal panel.