Philips MC-D370/22, Руководство по обслуживанию

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Name Number I/O Definition
MCLK 39 I/O Audio master clock for audio DAC.
TBCK 40 O Audio transmit bit clock.
SPDIF
41
O S/PDIF output.
SEL_PLL3 I Clock source select.
NC 42, 48 No connect pins. Leave open.
RSD 45 I Audio receive serial data.
RWS 46 I Audio receive frame sync.
RBCK 47 I Audio receive bit clock.
XIN 49 I Crystal input.
XOUT 50 O Crystal output.
AVEE 51 I Analog power for PLL.
DMA[11:0] 66:61, 58:53 O DRAM address bus [11:0].
DCAS# 69 O DRAM column address strobe.
DOE# 70 O DRAM output enable.
DSCK_EN O DRAM clock enable.
DWE# 71 O DRAM write enable.
DRAS# 72 O DRAM row address strobe.
DMBS0 73 O SDRAM bank select 0.
DMBS1 74 O SDRAM bank select 1.
DB[15:0] 96:93, 90:85,
82:77
I/O DRAM data bus [15:0].
DCS[1:0]# 97,100 O SDRAM chip select [1:0].
DQM 101 O Data input/output mask.
DSCK 102 O Output clock to SDRAM.
DCLK 105 I 27 MHz clock input to PLL.
YUV0
106
O YUV0 pixel output data.
CAMIN2 I Camera input 2.
UDAC O Video DAC output.
Y: Luma component for YUV and Y/C processing.
C: Chrominance signal for Y/C processing.
U: Chrominance component signal for YUV mode.
V: Chrominance component signal for YUV mode.
ES60x8 Pin Description (Continued)
SEL_PLL3 Clock Source
0 Crystal oscillator
1 DCLK input
Mode YDAC UDAC VDAC CDAC
A Y C Composite C
B Y Composite Composite C
C Y U Composite V
D Y U C V
9-7 9-7
DVD PROCESSOR
ES6028F DVD PROCESSOR
ES6028F
Name Number I/O Definition
YUV1 107 O YUV1 pixel output data.
VREF I Internal voltage reference to video DAC. Bypass to ground with 0.1 µ F capacitor.
YUV2
108
O YUV2 pixel output data.
CDAC O Video DAC output. Refer to description and matrix for UDAC pin 106.
YUV3 109 O YUV3 pixel output data.
COMP I Compensation input. Bypass to ADVEE with 0.1 µ F capacitor.
YUV4 110 O YUV4 pixel output data.
RSET I DAC current adjustment resistor input.
ADVEE 111 I Analog power for video DAC.
YUV5 113 O YUV5 pixel output data.
YDAC O Video DAC output. Refer to description and matrix for UDAC pin 106.
YUV6 114 O YUV6 pixel output data.
VDAC O Video DAC output. Refer to description and matrix for UDAC pin 106.
YUV7 115 O YUV7 pixel output data.
CAMIN3 I Camera YUV 3.
PCLK2XSCN 116 I/O 27-MHz video output pixel clock.
CAMIN4 I Camera YUV 4.
PCLKQSCN 117 O 13.5-MHz video output pixel clock.
CAMIN5 I Camera YUV 5.
VSYNC# 118 I/O Vertical sync, active low.
CAMIN6 I Camera YUV 6.
HSYNC# 119 I/O Horizontal sync, active low.
CAMIN7 I Camera YUV 7.
HD[5:0]
127:122
I/O Host data I/O [5:0].
DCI[5:0] I/O DVD channel data I/O [5:0].
AUX1[5:0] I/O Aux1 data I/O [5:0].
HD[6]
128
I/O Host data I/O [6].
DCI[6] I/O DVD channel data I/O [6].
AUX1[6] I/O Aux1 data I/O [6].
VFD_DOUT I VFD data output.
HD[7]
131
I/O Host data I/O [7].
DCI[7] I/O DVD channel data I/O [7].
AUX1[7] I/O Aux1 data I/O [7:0].
VFD_DIN I VFD data input.
HD[8]
132
I/O Host data bus 8.
DCI_FDS# I/O DVD input sector start.
AUX2[0] I/O Aux2 data I/O 0.
VFD_CLK I VFD clock input.
HD[9]
133
I/O Host data bus line 9.
AUX2[1] I/O Aux2 data I/O [1] when selected.
SQSQ I Subcode-Q data.
HD[10]
134
I/O Host data bus line10.
AUX2[2] I/O Aux2 data I/O [2] when selected.
SQSK I Subcode-Q clock.
ES60x8 Pin Description (Continued)