3 - 5
VSSE
_
E
B
I
F
1
7
Peripheral (I/O) ground
SAA7752 for
EBI pads
VSSE
_
E
B
I
L
1
4
Peripheral (I/O) ground
SAA7752 for
EBI pads
No
t
co
nne
c
ted p
ins
(fix
e
d
:
2
p
in
s)
NC
D15
Not connected
NC
A4
Not connected
NC
B2
Not connected
NC
A2
Not connected
NC
D17
Not connected
NC
D16
Not connected
NC
C15
Not connected
NC
C17
Not connected
NC
N4
Not connected
NC
P3
Not connected
NC
P2
Not connected
NC
P1
Not connected
NC
A6
Not connected
NC
B6
Not connected
NC
K2
Not connected
NC
E15
Not connected
NC
B3
Not connected
NC
A3
Not connected
NC
B4
Not connected
NC
B14
Not connected
NC
A15
Not connected
NC
B13
Not connected
NC
A14
Not connected
NC
E14
Not connected
NC
T17
Not connected
NC
U17
Not connected
NC
T16
Not connected
NC
R15
Not connected
NC
U16
Not connected
NC
M17
Not connected
NC
K17
Not connected
NC
H17
Not connected
NC
G17
Not connected
NC
J17
Not connected
NC
L17
Not connected
NC
N17
Not connected
NC
P14
Not connected
NC
R14
Not connected
NC
U15
Not connected
NC
T15
Not connected
NC
T14
Not connected
NC
N1
5
Not connected
NC
U14
Not connected
NC
C4
Not connected
SY
M
B
O
L
(1
)
LF
B
G
A
208
PI
N
DI
G
IT
A
L
I
/O L
E
V
E
L
A
PPL
.
FU
N
C
PI
N
S
TA
T
E
AF
TE
R
RESE
T
DE
S
C
R
IP
T
IO
N
EBI_D<1
1
>
T
4
0
-
3.3VDC tolerant
I/
O
EBI data
EBI_D<1
0
>
U
3
0
-
3.3VDC tolerant
I/
O
EBI data
EBI_D<9
>
T
3
0
-
3.3VDC tolerant
I/
O
EBI data
EBI_D<8
>
P
7
0
-
3.3VDC tolerant
I/
O
EBI data
EBI_D<7
>
U
2
0
-
3.3VDC tolerant
I/
O
EBI data
EBI_D<6
>
P
6
0
-
3.3VDC tolerant
I/
O
EBI data
EBI_D<5
>
U
1
0
-
3.3VDC tolerant
I/
O
EBI data
EBI_D<4
>
R
5
0
-
3.3VDC tolerant
I/
O
EBI data
EBI_D<3
>
T
2
0
-
3.3VDC tolerant
I/
O
EBI data
EBI_D<2
>
P
5
0
-
3.3VDC tolerant
I/
O
EBI data
EBI_D<1
>
T
1
0
-
3.3VDC tolerant
I/
O
EBI data
EBI_D<0
>
R
4
0
-
3.3VDC tolerant
I/
O
EBI data
EBI_S
DCLKOUT
J
1
O
SDRAM clock
EBI_
C
K
E
<
0
>
H
4
O
SDRAM clock enable
EBI_
D
Q
M
<
1
>
T
1
1
O
SDRAM data mask
1
EBI_DQM<0
>
U
1
1
O
SDRAM data mask
0
EBI_NRA
S
R
1
0
O
SDRAM
:
row address
strobe
SMC: byteWr0 (byte write enable for byte 0... active LOW)
EBI_NCA
S
R
1
1
O
SDRAM column address strob
e
SMC: byteWr1 (byte write enable for byte 1... active LOW)
EBI_N
O
E
H
2
O
EBI output enable
UA
RT
(fix
e
d
:
3
p
in
s
)
UART_
DIR_TX
D
1
0
O
UART_
REQ_RX
C
1
0
0
-
3.3VDC tolerant
I
UART_
C
L
K
D
1
1
0
-
3.3VDC tolerant
I/
O
Mo
de S
ele
c
tio
n
pi
n
s
S
A
A
7752
(fix
ed
: 3
pi
n
s
)
MODE<2
>
L
1
6
0
-
3.3VDC tolerant
I
MODE<1
>
M
1
5
0
-
3.3VDC tolerant
I
MODE<0
>
M
1
6
0
-
3.3VDC tolerant
I
Wa
ke
-u
p in
pu
t
pi
n
S
A
A
7752 (f
ix
e
d
:
1
pi
n
)
WAKE_UP
L
1
0
-
3.3VDC tolerant
I
Wake up input pin
Re
se
t
in
pu
t pi
n
S
A
A
7752
(fix
e
d
:
1
pi
n
)
N
RESET_
IN
L15
0
-
3.3VDC tolerant
I
System Reset Input
Re
se
t
ou
tp
ut
pi
n
SA
A
7752 (
fi
x
e
d
:
1
p
in
)
RESET_OUT
N
1
6
O
Reset output
Di
gi
ta
l s
upplie
s
S
A
A
7752
(fix
e
d
:
6
p
in
s)
VDDI1
L
4
Core supply
SAA7752
VSSIS1
L
3
Core ground and substrate
SAA7752
VDDI2
G
4
Core supply
SAA7752
VSSI2
G
3
Core ground
SAA7752
VDDI3
E
4
Core supply
SAA7752
VSSI3
E
3
Core ground
SAA7752
Pe
ri
ph
e
ra
l s
upplie
s
S
A
A
7752
(fix
e
d
:
4
p
in
s
)
V
DDE
3V3
J4
Peripheral (I/O) supply
SAA7752
(
3.3V)
VSSE3V3
K
4
Peripheral (I/O) ground
SAA7752
V
DDE
_
EBI
E1
7
Peripheral (I/O) supply
SAA7752
for EBI pads
V
DDE
_
EBI
K14
Peripheral (I/O) supply
SAA7752
for EBI pads
SY
M
B
O
L
(1
)
LF
B
G
A
208
PI
N
DI
G
IT
A
L
I
/O L
E
V
E
L
A
PPL
.
FU
N
C
PI
N
S
TA
T
E
AF
TE
R
RESE
T
DE
S
C
R
IP
T
IO
N
PIN DESCRIPTIONS OF IC SAA7752
Содержание eXpanium eXp 521
Страница 19: ...3 9 3 9 Headphone DC JACK BLOCKDIAGRAM ...
Страница 24: ...4 5 4 5 COMBI BOARD LAYOUT DIAGRAM COMPONENT SIDE VIEW ...
Страница 25: ...4 6 4 6 COMBI BOARD LAYOUT DIAGRAM COPPER SIDE VIEW ...