Philips eXpanium eXp 521, Руководство по обслуживанию

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3 - 4
CDB_NCRST_NHRD Y
D5
O
CD engine reset line/Host is ready to receive the next frame
CDB_C
L
A
B
C
9
0
-
3.3VDC toleran
t
I
IIS/EIAJ input bit clock
CDB_D
A
A
B
C
7
0
-
3.3VDC tolerant
I
IIS/EIAJ serial data
CDB_WSAB
C8
0- 3.3VDC tolerant
I
IIS/EIAJ word clock
CDB_E
F
A
B
D
9
0
-
3.3VDC toleran
t
I
IIS/EIAJ error flags
CDB_V
4
_
S
U
B
D
8
0
-
3.3VDC tolerant
I
Versatile pin 4:single wire subcode/EIAJ subcode data bits
CDB_C
FLAG
_
S
B
S
Y
D
6
0
-
3.3VDC tolerant
I
Absolute time sync/EIAJ subcode block sync
CDB_S
F
S
Y
D
7
0
-
3.3VDC tolerant
I
EIAJ
subcode
frame
sync
CDB_RCK
C
6
O
EIAJ subcode clock output
Audio DAC (SDAC, fixed 5 pins)
DAC_VREFP
R
1
7
a
n
alog positive reference for SDAC
DAC_REFN
P
1
6
analog
negative reference for SDAC
VOUTL
P
1
5
A
A
n
alog left LINE output
VOUTR
R
1
6
A
Analog right LINE output
DAC_VDD
N
1
4
I
Supply digital part of the SDAC
EB
I
(fix
e
d
: 4
9
p
in
s)
EBI_NCS<2>
G
1
6
O
Chip Selected 2
EBI_
N
C
S
<
1
>
T
1
0
O
Chip Selected 1
EBI_
N
C
S
<
0
>
U
1
0
O
Chip Selected 0
EBI_SDNCS
<
0
>
H
3
O
External SDRAM selection1 and SDRAM selection
0
EBI_
W
E
N
J
2
O
W
rite enable not
(for SDRAM only)
EBI_A<20>
J
1
6
I/
O
EBI address
EBI_A<19>
H
1
6
I/O
EBI address
EBI_
A
<
1
8>
F
1
4
O
EBI address
EBI_A<17
>
G
1
4
O
EBI address
EBI_A<16
>
H
1
4
O
EBI address
EBI_A<15
>
J
1
4
O
EBI address
EBI_A<14
>
R
9
O
EBI address
EBI_A<13
>
T
9
O
EBI address
EBI_A<12
>
U
9
O
EBI address
EBI_A<11
>
R
8
O
EBI address
EBI_A<10
>
T
8
O
EBI address
EBI_A<
9
>
U
8
O
EBI address
EBI_A<
8
>
P
1
1
O
EBI address
EBI_A<
7
>
R
7
O
EBI address
EBI_A<
6
>
P
1
0
O
EBI address
EBI_A<
5
>
U
7
O
EBI address
EBI_A<
4
>
P
9
O
EBI address
EBI_A<
3
>
T
7
O
EBI address
EBI_A<
2
>
P
8
O
EBI address
EBI_A<1>
R
6
O
EBI address
EBI_A<
0
>
U
6
O
EBI address
EBI_
D
<
1
5
>
T
6
0
-
3.3VDC tolerant
I/
O
EBI data
EBI_D<1
4
>
U
5
0
-
3.3VDC tolerant
I/
O
EBI data
EBI_D<1
3
>
T
5
0
-
3.3VDC tolerant
I/
O
EBI data
EBI_D<1
2
>
U
4
0
-
3.3VDC tolerant
I/
O
EBI data
SY
M
B
O
L
(1
)
LF
B
G
A
208 PI
N
DI
G
IT
A
L
I
/O L
E
V
E
L
A
PPL
.
FU
N
C
PI
N
S
TA
T
E
AF
TE
R
RESE
T
DE
S
C
R
IP
T
IO
N
LCD_
E_RD
B
1
5
O
6800 active ‘low’ enable 8080 active ‘high’ write enable
LCD_
D
B
<
0
>
D
1
4
0
-
3.3VDC tolerant
I/O
Data input 0/Data output
0
LCD_
D
B
<
1
>
B
1
7
0
-
3.3VDC tolerant
I/O
Data input 1/Data output
1
LCD_
D
B
<
2
>
C
1
4
0
-
3.3VDC tolerant
I/O
Data input 2/Data output
2
LCD_
D
B
<
3
>
C
1
6
0
-
3.3VDC tolerant
I/O
Data input 3/Data output
3
LCD_
D
B
<
4
>
D
1
3
0
-
3.3VDC tolerant
I/O
Data input 4/Data output
4
LCD_
D
B
<
5
>
A
1
7
0
-
3.3VDC tolerant
I/O
Data input 5/Data output 5/serial clock
LCD_
D
B
<
6
>
C
1
3
0
-
3.3VDC tolerant
I/
O
Data input 6/Data output 6/Serial data input
LCD_
D
B
<
7
>
B
1
6
0
-
3.3VDC tolerant
I/
O
Data
input
7/Data
output
7/Serial
data
output
LCD_
C
S
B
C
1
2
O
Chip Select (active low)
LCD_
R
S
D
1
2
O
‘high’ Data register select ‘low’ Instruction register select
10-
bi
t A
D
C
(fix
e
d
:
9
p
in
s)
GPA<4>
A
5
A
A
nalog General Purpose pin 4
GPA<3>
B
5
A
Analog General Purpose pin
3
GPA<2>
J
3
A
Analog General Purpose pin
2
GPA
<1
>M
4A
Analog General Purpose pin
1
GPA
<0>
N3
AA
nalog General Purpose pin
0
VREFP
<
1
>
M
3
A
10-bit ADC Reference voltage
1
VREFP
<
0
>
L
2
A
10-bit ADC Reference voltage
0
VDDA
4
M
2
A
nalog supply 10-bit ADC
VSS
A4
M1
Analog ground 10-bit ADC
IIS
in
pu
t (fix
e
d
:
3
pi
n
s
)
BCKI
1
J
1
5
0
-
3.3VDC toleran
t
I
Bitclock input (external)
WSI
1
H15
0- 3.3VDC tolerant
I
Wordselect input
(external)
D
ATAI
1
G
1
5
0
-
3.3VDC tolerant
I
Serial data input
(external)
IIS
ou
tp
ut
(fix
e
d
: 3
pi
n
s
)
BCKO
1
M14
I/
O
Tri-state
Bitclock output
(external)
WSO
1
F16
O
Tri-state
Wordselect output
(external)
D
ATAO
1
E
1
6
O
Output/Low
Serial data output
(external)
JT
AG
(fix
e
d
:
5
p
in
s
)
JTAG_NTRST
K
1
5
0
-
3.3VDC tolerant
I
JTAG Reset Input
JTAG_TCK
U12
0- 3.3VDC tolerant
I
JTAG Clock Input
JTAG_
T
M
S
K
1
6
0
-
3.3VDC toleran
t
I
JTAG Mode Select Input
JTAG_
T
D
I
T
1
3
0
-
3.3VDC tolerant
I
JTAG Data Input
JTAG_
T
D
O
U
1
3
O
JTAG Data Output
IIC
sl
av
e
In
te
rf
ac
e
(fix
e
d
: 3
p
in
s
)
SCL_SLAVE
P
1
2
0-
3.3VDC tolerant
I/
O
Serial clock IIC Slave
SDA_SLAVE
R
1
2
0-
3.3VDC tolerant
I/
O
Serial data IIC Slave
A0_SLAVE
T
1
2
0- 3.3VDC tolerant
I
Address selection Slave
IIC
ma
st
er
in
te
rf
a
c
e
(fix
e
d
:
2
p
in
s)
SD
A
_MASTER
R
1
3
0-
3.3VDC tolerant
I/
O
IIC data I/O line (open drain output)/ UART Serial Data Input
SCL_MASTER
P
1
3
0
-
3.3VDC tolerant
I/
O
IIC clock line output/ UART Serial Data Output
CD
B
lo
c
k
D
e
c
o
de
r
(fix
e
d
:
10
p
in
s)
CDB_CRQ_NERDY
C
5
0- 3.3VDC toleran
t
I
Communication request line/CD engine is ready to receive the next frame
SY
M
B
O
L
(1
)
LF
B
G
A
208 PI
N
DI
G
IT
A
L
I
/O L
E
V
E
L
A
PPL
.
FU
N
C
PI
N
S
TA
T
E
AF
TE
R
RESE
T
DE
S
C
R
IP
T
IO
N
PIN DESCRIPTIONS OF IC SAA7752