Philips EM5E, Руководство по обслуживанию, Страница: 116 / 136

Circuit Descriptions and Abbreviation List EN 116 EM5E 9.
CRT and on the V
SYNC
from the HOP, for the synchronisation
of TXT/OSD/EPG
When no CVBS is offered to the video processor, the V
A50
and
H
A50
pulses are switched 'off' by the HIP, and the pulses are
generated by the PICNIC (to assure a stable OSD).
9.10 Horizontal (Line) Deflection (Diagram A3)
9.10.1 Principle
Figure 9-16 Line deflection circuitry
The HOP (located on the SSB) generates the line-drive pulses
(LINEDRIVE1), which have a frequency of 31250 Hz
(T = 32
µ
s).
When the LINEDRIVE1 signal is high, TS7409 and TS7408 will
conduct. A constant DC voltage will be applied across L5410,
causing a linear increasing current through this coil. The
secondary voltage of L5410 has a negative polarity so that
TS7421 will block.
When the set is switched 'on', the current through L5410 is
supplied by the 5V2 Standby supply (via D6407), and taken
over by the +11D voltage (via D6408) of the main supply.
When the LINEDRIVE1 signal becomes low, TS7409 and
TS7408 will block. The voltage polarity across the primary
winding of L5410 will invert. The positive voltage on the
secondary winding will now drive TS7421 into conductivity.
Because of the storage time of the line transistor (TS7421),
L5410 cannot transfer its energy immediately to the secondary
side. This may result in high voltage peaks on the collector of
TS7409 and TS7408. To prevent that these peaks will damage
the transistors, a 'snubber' circuit (C2414, C2412 and R3411)
will suppress them.
When the LINEDRIVE1 signal is high again, the above
described sequence starts again. Circuit L5411 and R3409 will
increase the switch 'off' time of the line transistor.
The line stage is started via a 'slow start' principle. During start-
up, the HOP generates line drive pulses with a small T
ON
and a
high frequency (50 kHz). T
OFF
is constant and T
ON
is gradually
increased until the frequency is 31250 Hz (normal condition).
The time interval from start to normal condition takes about 150
ms.
When switching off, the same procedure is followed, but now in
reverse order.
9.10.2 Implementation
To explain the operation of the line output stage, we use the
following start conditions:
•
C2433 is charged to max. 141 V (V
BAT
)
• TS7421 is driven into conductivity.
CL 26532041_077.eps
170402
3481
6480 2426 6422
2421
7480
ARC
PROT
3414
2415
6406
3406
3431
2430
1417
5421
2431
141V
141V
7482
3418
3488
HOT COLD
2425 6423
2433
6408
6407
3416
3409
5411
2414
5410
3411
2412
7408
+8VB
+8VS
7409
MAIN 11D
STANDBY 5V2
2492
3407
3487
2420
7421
5430
2417
3417
3486
2
1
3412
6615
3404
LINEDRIVE 1
(HOP)
EW_DRIVE
(HOP)
ST
AR
T
NORMAL
T7421 conducting
TON
TOFF
1
2
5
*1
*2
(*1)
(*2)
1
2
1
4
3
LINE
DEFL. COIL.
LINEARITY
COIL.
5422
Caused by
serial losses in
the line output stage
Linearity Correction
S-correction
X
Y X
Deflection centre
X > Y
3 5
7450-B
8
4
2
1 5
4
6
3490
3484
3492
7487
7486
3483 3479