Philips DVDR70/001, Руководство по обслуживанию

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Circuit-, IC descriptions and list of abbreviations EN 242 DVDR70 & DVDR75/0x1 9.
FBIN ............................. Fast Blanking input
FOME ........................... FOllow ME Status line (matching
signals yes/no; only for Europe)
G1…10 ......................... DISPLAY GRID
INT................................ Interrupt OUT for the CC
INT................................ Interrupt – line from Display Print
ION ............................... Inverse ON-Line
IPFAIL .......................... Inverse Power Fail Detection
IPOR............................. Inverse Power On Reset
IRESET ........................ Inverse Reset Input
IRR ............................... Signal from IR-Receiver
K1 ................................. Key-Input-Line
K2 ................................. Key-Input-Line
KILL .............................. Audio Mute
P50 IN .......................... P50 INput-line (only for Europe)
P50 OUT ...................... P50 OUTput-line (only for Europe)
POR_DC ...................... Power On Reset for Display Control
Print (Ext_DL)
PSS .............................. Pal/Secam-Select
PWM_FIL ..................... Control line for Filament Voltage
Generation
PWONSW .................... Amplifier Switch Audio A/D Converter
RD_ .............................. Output Enable ReaD (CC - Flash-
ROM and S-RAM)
RECLED....................... Control Signal for REC-LED
RESET_DIG ................. Reset Line to Digital Board
RP_ .............................. Inverse Reset line to Flash-ROM
RSA1/2 ......................... Record Selector 1/2
RY/BY_......................... Ready/Busy – input line (from Flash-
ROM)
SIF1.............................. Sound intermediate frequency
SB1............................... Secam Band 1 (PCB-Test entrance)
SCL .............................. I²C-Bus
SCLSW......................... Switched I²C-Bus
SDA .............................. I²C-Bus
SDASW ........................ Switched I²C-Bus
SFS_TS........................ SAW Filter Select Trap Select
STBY ............................ Standby-Line (Flash_Toshiba)
SYNC ........................... Video Sync input
TEMP_SENSE ............. Temperature Sense Line
VER .............................. HW-version input
VFV .............................. Video from Frontend
VKK .............................. VFT Driver Power Supply
VREFH ......................... Pin for Reference-voltage input to A/D-
converter
VREFL.......................... Pin for Reference-voltage input to A/D-
converter
VS1/2............................ View Selector 1/2
WR_ ............................. Write Enable (CC - Flash-ROM and S-
RAM)
WSFI ............................ Wide Screen Signalling Front In
WU ............................... Wake Up
X1 ................................. Oscillator Pin
X2 ................................. Oscillator Pin
XIN ............................... Oscillator Pin
XOUT ........................... Oscillator Pin
XT1............................... Low Frequency Oscillator Pin
XT2............................... Low Frequency Oscillator Pin
YFIN ............................. Luminance Front In
Digital Board
+12V ............................. +12V Power Supply
+2V5_FLI...................... +2V5 Power Supply for FLI
+2V5_PLL .................... +2V5 Power Supply for PLL
+3V3 ............................. +3V3 Power Supply
+3V3_ANA ................... +3V3 Power Supply Analogue
+3V3_DD...................... +3V3 Power Supply Digital
+3V3_FLI...................... +3V3 Power Supply for FLI
+5V ............................... +5V Power Supply
+5V_BUFFER .............. +5V Power Supply for Video Filters
5508_HS ...................... Horizontal Synchronisation from Host
Decoder to Progressive Scan
5508_ODD_EVEN ....... Odd - Even control from Host Decoder
to Progressive Scan
-5V ............................... -5V Power Supply
-5V_BUFFER ............... -5V Power Supply for Video Filters
A_EMPRESS(13:0)...... EMPRESS address output to SDRAM
ACC_ACLK_OSC ........ Audio Clock PLL output sync with
incoming video for record
ACC_ACLK_PLL.......... Audio Clock PLL output for play back
ACLK_EMP.................. EMPRESS audio clock output
AD_ACLK..................... Audio Decoder Clock
AD_BCLK..................... Audio Decoder I2S bit clock
AD_DATAO.................. Audio Decoder Output data (PCM)
AD_SPDIF33 ............... Audio digital output to the analog
board
AD_WCLK.................... Audio Decoder I2S word clock
AE_ACLK..................... Audio Encoder Clock
AE_ACLK_OEN ........... Audio Encoder Clock Output Enable
AE_BCLK..................... Audio Encoder I2S bit clock
AE_BCLK_DV .............. Audio Encoder I2S bit clock to DVIO
AE_BCLK_VSM ........... Audio Encoder I2S bit clock to VSM
AE_DATAI.................... Audio Encoder Input data (PCM)
AE_DATAI_DV............. Audio Encoder Input data (PCM) from
DVIO
AE_DATAO .................. Audio Encoder Output data (PCM)
AE_WCLK.................... Audio Encoder I2S word clock
AE_WCLK_DV ............. Audio Encoder I2S word clock to DVIO
AE_WCLK_VSM .......... Audio Encoder I2S word clock to VSM
ANA_WE...................... Analogue write enable
ANA_WE_LV ............... Analogue write enable Low Voltage
B_IN_VIP ..................... Video blue input to Video Input
Processor
B_OUT ......................... Video blue output from Host Decoder
B_OUT_B..................... Filtered blue video output
BA ................................ Bank Address
BCLK_CTL_SERVICE . Bitclock control Service Interface
BE_BCLK..................... Basic Engine I2S bit clock
BE_BCLK_VSM ........... Basic Engine I2S bit clock to VSM
BE_CPR....................... Basic Engine Control Processor ready
to accept data
BE_DATA_RD ............. Basic Engine Data read
BE_DATA_WR............. Basic Engine Data write
BE_FAN ....................... Basic Engine FAN
BE_FLAG ..................... Basic Engine error flag
BE_IRQN ..................... Basic Engine interrupt request
BE_LOADN.................. Basic Engine LOAD(LOW active)
BE_RXD....................... Basic Engine S2B received data
BE_SUR....................... Basic Engine servo unit ready to
accept data (S2B)
BE_SYNC .................... Basic Engine sector/abs time sync
BE_TXD ....................... Basic Engine S2B transmitted data
BE_V4.......................... Basic Engine versatile input pin
BE_WCLK .................... Basic Engine I2S word clock
C_IN ............................. Video Chrominance input
C_IN_VIP ..................... Chrominance input to Video Input
Processor
C_OUT ......................... Chrominance output from Host
Decoder
C_OUT_B .................... Filtered Chrominance output
CAS.............................. Column Address strobe
CB_OUT(9:0) ............... Chrominance Blue out
CLK4 ............................ SDRAM clock
CPUINT0...................... Control processor unit interrupt
CPUINT1...................... Control processor unit interrupt
CR_OUT(9:0) ............... Chrominance Red out
CTS1P ......................... Clear to send (Service Interface)
CVBS_OUT.................. Composite video output out of the
Host Decoder
CVBS_OUT_B ............. Filtered Composite video output
CVBS_OUT_B_VIP ..... Composite video output to Video Input
Processor(digital board video loop)
CVBS_Y_IN ................. Composite video/Luminance input
CVBS_Y_IN_A ............. Composite video/Luminance input to
Video Input Processor
CVBS_Y_IN_B ............. Composite video/Luminance input to
Video Input Processor