Philips A02U AA, Руководство по обслуживанию

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Circuit Descriptions, Abbreviation List, and IC Data Sheets EN 101 A02U AA 9.
will appear to behave and to look like "STANDBY" mode to the
user. The user is totally oblivious of the existence of this mode.
The status of the power supply lines and the estimated total
power consumption of the SSB are the same as "ON" mode.
In this mode, the ADOC ICs horizontal deflection drive output
is disabled, while the STANDBY control port is disabled. This
consequently causes the LOT stage on the LSP to be inactive
(although V_batt voltage is present) that, in turn, will cause the
EHT to be cut off. This in turn will cause the CRT display to be
inactive.
From this mode, it is possible to transit to "ON" mode,
"STANDBY" mode, "PROTECTION" mode or "OFF" mode.
PROTECTION Mode
Power profile for protection mode is as low as required to allow
"soft" diagnostics, error detection, and to indicate LED flashes
to flag the type of fault. The horizontal deflection is "off" in this
mode. From the protection mode, the only possible transition is
to "OFF" mode.
9.3.3
Start Up Sequence
1.
When we start the set (cold start), initially 5V2, 3V3, and
1V8 will be available. These come from the Standby
module of the power supply.
2.
After this, the microprocessor resets (tied to 1V8 and 3V3
supplies) and checks the last status of the supply from the
NVM. Accordingly, the set will be put in "STANDBY" or in
the normal "on" condition.
3.
Now, 5V and 8V are available if the last status was "on"
condition, and the DOP is initialized by the microcontroller
through the PI bus (not via the I2C).
4.
The H-drive will become available from the DOP, which is
the source for the "SUP_ENABLE" signal.
5.
Via the "SUP-ENABLE" signal, the Main Supply is switched
"on" and will deliver the V_BAT to the Line deflection stage.
6.
EHT generation is now started.
7.
The uP will un-blank the picture.
8.
When you switch "off" the set, this is done in a controlled
way via the POR (Power On Reset) signal.
Note: Standby is controlled by the STANDBY Line of the uP
(not by the DOP).
9.3.4
Shut Down Sequence
This section describes the processes that need to be handled
by hardware and software when power is disconnected from
the set.
Some system requirements:
•
To handle CRT discharge.
•
To handle "switch off" plops.
•
To prevent NVM corruption at switch "off".
•
To effectively distinguish between the condition of mains
interruptions and shutdown and handle them properly.
•
The "power down" detection is acquired from the deflection
supply (+11V) and the level is translated to +3.3V (this
event has the highest interrupt priority to trigger SW
shutdown procedure).
•
Power down detection is fed to the FBCIN input, initiates a
slow stop, and hence ensures CRT discharge (it is
important that the slow-stop is maintained for at least 50
ms to assist good discharge).
•
The microcontroller, hence the system, shall have a clean
power "on" and power "off" reset with respect to its supply.
The microcontroller shall not be operational when the
supply voltage is below the recommended limits. The
transition between active and reset is fast.
•
The microcontroller "off" reset must occur much later (> 45
ms) than the POWER DOWN signal (P.DN).
When the POWER DOWN interrupt occurs, there is no way of
knowing whether it is due to Medium Mains Interruptions or due
to shutdown. Hence, there is no choice but to initiate shutdown
procedure as described further below. The definition of Mains
Interruption is given below:
•
Short Mains Interruptions. Duration of the interrupts <=
55 ms. The set shall continue to work properly. The "power
off" acquisition circuit shall filter such events.
•
Medium Mains Interruptions. Interruptions are of the
order 70 to 80 ms. This is a typical situation when the
"power off" acquisition circuit, signals that the power is
going down but the microcontroller does not get a reset. In
this condition, a POWER DOWN signal is generated but no
POWER OFF RESET signal is available.
•
Long Mains Interruption or Shutdown. Any interrupt
above 80 ms shall cause a microcontroller reset and hence
a cold start. This happens, when the power is disconnected
long enough to get a "Power Off Reset" as well as the
microcontroller reset. After this situation, the system would
automatically cold start when the power resumes.
Figure 9-4 Shut down block diagram
Shutdown Procedure
1.
Exclude all processes and do not respond to any interrupts
- including RC events. However, during the following
defined conditions of stopping the deflection (DFL-bit= 0),
ignore the P.DN interrupt and rest of the procedure:
–
The system switched from ON to Standby by the user.
–
Protection event that forces the H-Deflection to stop.
–
Any other SW controlled event that causes the
deflection to stop.
2.
Since the P.DN signal is connected to FBCIN input, the
DOP shall slow stop immediately - no software intervention
is required. The precondition for this is that the FBDM bit in
DOP is set to "1". The slow -stop process will continue for
the next 40 ms or so.
3.
Mute Audio Output / Sound Enable line.
4.
Mute audio external outputs (in ADOC).
5.
Set the DFL-bit to "0", such that deflection shall not restart
after the slow -stop process is done.
6.
Disable NVM access. Do the following:
–
Put the NVM in standby state to stop I2C write to NVM,
by sending the Universal Reset Sequence.
–
Set Write Enable high: this avoids any further Write
sequence to the NVM.
7.
Disable all the I2C hardware communication.
8.
Wait for 200 ms and execute a cold start when there is no
microcontroller-reset signal. This is considered as
"medium mains interruption".
9.
After the cold start, the set should resume to the last status
of user settings.
POWER-DOWN
DETECTION
A D O C I C
FBCIN
POWER-DOWN
Interrupt (P0_1|INT1)
+11V
(LOT)
UP RESET
Generator
+5V2
STANDBY
SUPPLY
P.DN signal
(POR_FLASH)
uP RESET
Signal
RESET
CL 36532058_081.eps
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