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Circuit Descriptions, Abbreviation List, and IC Data Sheets
9.
9.4.4
Diagram B4A, SSTP39VF088
Figure 9-6 Internal block diagram and pin configuration
Block Diagram
Pin Configuration
H_17360_056.eps
140907
Y-Decoder
I/O Buffers and Data Latches
Address Buffer & Latches
X-Decoder
DQ7 - DQ0
Memory
Address
OE#
CE#
WE#
SuperFlash
Memory
Control Logic
A16
A15
A14
A13
A12
A11
A10
A9
NC
NC
WE#
NC
NC
NC
NC
A19
A18
A8
A7
A6
A5
A4
A3
A2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A17
NC
VSS
A0
DQ7
NC
DQ6
NC
DQ5
NC
DQ4
VDD
NC
DQ3
NC
DQ2
NC
DQ1
NC
DQ0
OE#
VSS
CE#
A1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Standard Pinout
Top View
Die Up