Philips 32HF7445/93, Руководство по обслуживанию

Страница: 68 / 77

江南家电维修论坛会员专用！
http://bbs.520101.com
Circuit Descriptions, Abbreviation List, and IC Data Sheets EN 68 TPT1.1HA LA 9.
9.4.2 Diagram B2A, M16C/62P
Figure 9-4 Internal block diagram and pin configuration
Block Diagram
Pin Configuration
H_17360_054.eps
140907
Timer (16-bit)
Output (timer A): 5
Input (timer B): 6
Internal peripheral functions
Watchdog timer
(15 bits)
DMAC
(2 channels)
D-A converter
(8 bits X 2 channels)
A-D converter
(10 bits
X
8 channels
Expandable up to 26 channels)
UART or
clock synchronous serial I/O
(8 bits
X
3 channels)
System clock generator
X
IN
-X
OUT
X
CIN
-X
COUT
PLL frequency synthesizer
Ring oscillator
M16C/60 series16-bit CPU core
Port P0
8
Port P1
8
Port P2
8
Port P3
8
Port P4
8
Port P5
8
Port P6
8
CRC arithmetic circuit (CCITT )
(Polynomial : X
16
+X
12
+X
5
+1)
Memory
8
7
8
8
0
1
P
tr
o
P
9
P
tr
o
P
8
P
tr
o
P
7
P
tr
o
P
8
P
tr
o
P
5
ROM
(Note 1)
RAM
(Note 2)
Note 1: ROM size depends on microcomputer type.
Note 2: RAM size depends on microcomputer type.
Note 3: Ports P11 to P14 exist only in 128-pin version.
Clock synchronous serial I/O
(8 bits
X
2 channels)
R0L R0H
R1H
R1L
R2
R3
SB
FLG
USP
ISP
INTB
PC
Multiplier
Port P11
8
Port P14
2
Port P12
8
Port P13
8
Three-phase motor
control circuit
A0
A1
FB
<V
CC2
ports>
(Note 3) (Note 3) (Note 3) (Note 3)
<V
CC1
ports>
V
<
1
C
C
>
st
r
o
p
<V
CC1
ports> <V
CC2
ports>
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P0
0
/AN
00
/D
0
P0
1
/AN
01
/D
1
P0
2
/AN
02
/D
2
P0
3
/AN
03
/D
3
P0
4
/AN
04
/D
4
P0
5
/AN
05
/D
5
P0
6
/AN
06
/D
6
P0
7
/AN
07
/D
7
P1
0
D/
8
P1
1
D/
9
P1
2
D/
0
1
P1
3
D/
1
1
P1
4
D/
2
1
V
REF
AV
SS
V
1
C
C
X
NI
X
T
U
O V
SS
T
E
S
E
R
s
s
V
N
C
P8
7
X/
NI
C
P8
6
X/
T
U
O
C
E
T
Y
B
P2
0
N
A/
0
2
A/
0
D/
(
0
)-/
P2
1
N
A/
1
2
A/
1
D/
(
1
D/
0
)
P2
2
N
A/
2
2
A/
2
D/
(
2
D/
1
)
P2
3
N
A/
3
2
A/
3
D/
(
3
D/
2
)
P2
4
N
A/
4
2
A/
4
D/
(
4
D/
3
)
2
P
5
N
A/
5
2
A/
5
D/
(
5
D/
4
)
P2
6
N
A/
6
2
A/
6
D/
(
6
D/
5
)
P2
7
N
A/
7
2
A/
7
D/
(
7
D/
6
)
3
P
0
A/
8
D/
-/
(
7
)
P3
1
A/
9
P3
2
A/
0
1
P3
3
A/
1
1
P3
4
A/
2
1
P3
5
A/
3
1
P3
6
A/
4
1
P3
7
A/
5
1
P4
0
A/
6
1
P4
1
A/
7
1
4
P
2
A/
8
1
P4
3
A/
9
1
P7
4
2
A
T/
T
U
O
W/
P7
6
3
A
T/
T
U
O
P5
6
/ALE
P7
7
3
A
T/
NI
P5
5
/HOLD
P5
4
/HLDA
P5
3
/BCLK
P5
2
/RD
V
2
C
C
V
SS
P5
7
/RDY/CLK
OUT
P4
5
/CS1
P4
6
/CS2
P4
7
/CS3
AV
CC
P6
3
/T
X
D
0
/SDA
0
P6
5
/CLK
1
P6
6
/RxD
1
/SCL
1
P6
7
/T
X
D
1
/SDA
1
P6
1
/CLK
0
P6
2
/RxD
0
/SCL
0
P10
0
/AN
0
P10
1
/AN
1
P10
2
/AN
2
P10
3
/AN
3
P9
3
A
D/
0
3
B
T/
NI
P9
4
A
D/
1
4
B
T/
NI
9
P
5
4
K
L
C/
0
X
E
N
A/
P9
6
S/
1
X
E
N
A/
T
U
O
4
P9
1
1
B
T/
NI
S/
NI
3
P9
2
2
B
T/
NI
S/
T
U
O
3
P8
0
4
A
T/
T
U
O
U/
P6
0
/CTS
0
/RTS
0
P6
4
/CTS
1
/RTS
1
/CTS
0
/CLKS
1
P7
2
K
L
C/
2
1
A
T/
T
U
O
V/
P8
2
T
NI/
0
P7
1
D
x
R/
2
L
C
S/
2
0
A
T/
NI
5
B
T/
NI
)
et
o
N(
P8
3
T
NI/
1
P8
5
I
M
N/
P9
7
/AD
TRG
/S
IN
4
P4
4
/CS0
P5
0
/WRL/WR
P5
1
/WRH/BHE
9
P
0
0
B
T/
NI
3
K
L
C/
P7
0
T/
X
D
2
A
D
S/
2
0
A
T/
T
U
O
)
et
o
N(
8
P
4
T
NI/
2
P8
1
4
A
T/
NI
U/
7
P
3
S
T
C/
2
S
T
R/
2
1
A
T/
NI
V/
P7
5
2
A
T/
NI
W/
P1
5
D/
3
1
3
T
NI/
1
P
6
D/
4
1
4
T
NI/
P1
7
D/
5
1
5
T
NI/
P10
7
/AN
7
/KI
3
P10
6
/AN
6
/KI
2
P10
5
/AN
5
/KI
1
P10
4
/AN
4/
KI
0
Package: 100P6S-A
M16C/62P Group
Note: P70 and P7
1
are N channel open-drain output pins.