IC Data Sheets
8.
8.4
Diagram
B04, TMDS361BPAGR (IC U501)
Figure 8-5 Internal block diagram and pin configuration
19160_304_110622.eps
110622
Block diagram
Pinning information
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SDA3
SCL3
GND
CLK–_3
CLK+_3
VCC
D0–_3
D0+_3
GND
D1–_3
D1+_3
VCC
D2–_3
D2+_3
GND
VSadj
7
1
8
1
9
1
0
2
2
1
2
2
3
2
4
2
5
2
6
2
7
2
8
2
2
9
0
3
1
3
2
3
S
_
+
2
D K
N I
2
D
K
N I
S
_
–
C
C
V
N I
S
_
+
1
D K
N I
S
_
–
1
D K
N
G D
_
+
0
D K
N I
S
N I
S
_
–
0
D K
C
V C
L
C K
N I
S
_
+
K
S
_
–
K
L
C K
N I
G
D
N
_
L
C
S
K
N I
S
I
S
_
A
D
S
K
N
S
_
D
P
H K
N I
1
S
L
C
S
/
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
D2+_1
D2–_1
VCC
D1+_1
D1–_1
GND
D0+_1
D0–_1
VCC
CLK+_1
CLK–_1
SCL1
SDA1
HPD1
I2C_SEL
S2/SDA
4
6
3
6
2
6
1
6
0
6
9
5
8
5
7
5
6
5
5
5
4
5
5
3
2
5
1
5
0
5
9
4
D
P
H
3
+
2
D 2
_
2
_
–
2
D
V
C
C
+
1
D 2
_
2
_
–
1
D
D
N
G
+
0
D
2
_
2
_
–
0
D
V
C
C
K
L
C 2
_
+
K
L
C 2
_
–
2
L
C
S
S
2
A
D
D
P
H
2
P
L
TMDS361B
64-pin TQFP
HPD_SINK
V
cc
R
INT
Clock Detect
R
INT
V
cc
R
INT
TMDS Rx
R
INT
V
cc
R
INT
Clock Detect
R
INT
V
cc
R
INT
TMDS Rx
R
INT
Dx+_1
Dx–_1
CLK+_1
CLK–_1
Dx+_3
Dx–_3
CLK+_3
CLK–_3
xx2
Rx
Tx
Rx
Tx
SCL1
SDA1
Rx
Tx
Rx
Tx
SCL3
SDA3
HPD1
HPD2
HPD3
VSadj
Dx+_SINK
Dx–_SINK
CLK+_SINK
CLK–_SINK
TMDS Tx
TMDS Tx
Tx
Rx
Tx
Rx
SDA_SINK
SCL_SINK
S1/SCL
S2/SDA
I2C_SEL
Clock Detect
LP
TMDS Rx
w/ AEQ
TMDS Rx
w/ AEQ
3:1
MUX
and
2