GRL-PCIE-TX Quick Start/User Guide/MOI
Rev1.0
© PCI-SIG 2022
Version 1.0, Mar 2022. Updated 03.26.2022
Page.
44
7.7
System Board Ref Clock (100 MHz) Jitter Test
Note: Make sure to terminate lanes that are not being tested with 50-ohm MMPX terminators.
1.
Set up the test equipment as described in Section 4.2.3.
2.
Adjust the Scope to capture >80K Clock Cycle (80000 * 10 ns = 0.8 ms).
3.
SSC can be turned ON or OFF depending on the system board DUT.
4.
Using the Clock Jitter Tool, measure the HF RJ RMS (Max Phase Jitter) as shown in figure
below.
5.
The test is considered as Pass if the HF RJ RMS (Max Phase Jitter) is
≤
200 fs.
