GRL-PCIE-TX Quick Start/User Guide/MOI
Rev1.0
© PCI-SIG 2022
Version 1.0, Mar 2022. Updated 03.26.2022
Page.
42
6.
Measure UPW-TJ, UPW-DJDD, UTJ, and UDJDD @1e-12 on SigTest Phoenix using the
“
Templates\PCIe\5_0\Base\Optimize_CTLE
”
template file and select
Test
to start the
measurements.
7.
The test is considered as Pass if the following target jitter parameter values are met:
•
UPW-
TJ ≤ 6.25 ps
•
UPW-
DJDD ≤ 2.5 ps
•
UTJ ≤ 6.25 ps
•
UDJDD ≤ 3.125 ps
7.6
Add-In Card Tx Base Jitter (UPW-TJ, UPW-DJDD, UTJ and UDJDD) Test
Note: Make sure to terminate lanes that are not being tested with 50-ohm MMPX terminators.
1.
Set up the test equipment as described in Section 4.2.2.
2.
Adjust the Scope to capture 2M UI
’s
with the following configuration:
•
Bandwidth: 33 GHz
•
Sampling Rate: ≥ 128
GS/s
•
No embedding
3.
Turn on SSC on the CBB (-0.5% SSC down-spread).
4.
Push the compliance toggle on the DUT to transmit 32 GT/s Jitter Measurement pattern
(setting #47 on Lane 0 in the PCIe 5.0 Base Specification and COMPAT on adjacent lanes) by
injecting 1 ms pulse of 100 MHz clock signal into Rx Lane 0.
5.
On the Scope, capture 2.0M UI
’s
and save the captured waveforms to be used for post-
processing.
6.
To measure UPW-TJ, UPW-DJDD, UTJ, and UDJDD, load the saved waveform files in SigTest
Phoenix (by selecting
PCIe
→
5_0
→
Base
→
Browse
→
Load and Verify Data
).
7.
Measure UPW-TJ, UPW-DJDD, UTJ, and UDJDD @1e-12 on SigTest Phoenix using the
“
Templates\PCIe\5_0\Base\Optimize_CTLE
”
template file and select
Test
to start the
measurements.
