ER
(Flashing Red) - blinks ON/OFF after a 511/511E
test has timed out. See Section 5.3.3 (Test
Pattern Generator) for more information.
- flashes once to indicate that a CRC error has
occurred (during normal operation) or bit errors
have occurred (during 511/511E tests).
- Only at power up, blinks once every 200 ms if
the DTE Rate is set to an unsupported settings
TM (Active
Yellow) glows yellow to indicate that the
Model 1088/K has been placed in Test Mode. The
unit can be placed in test mode by the local user
or by the remote user. The TM LED will flash for
400msec when a valid packet is received from the
Model 1001MC.
5.3 TEST MODES
The Model 1088 offers two proprietary loopback test modes, plus
a built-in V.52 BER test pattern generator to evaluate the condition of
the modems and the communication link. These tests can be activat-
ed physically from the front panel.
5.3.1 Overview
Figure 11 below shows the major elements used in the loop-back
and pattern tests available in the Model 1088. Each block has several
functions. Following Figure 11 are descriptions that show how the ele-
ments are used during Test Modes.
19
Framer
The framer is used to determine the status of
the line. In normal operation the framer trans-
mits and expects to receive framed packets
from the far end. If the framer receives framed
packets from the far end, the DSL Link LED will
be active. If framed packets are not received,
the DSL Link LED will be inactive. The restart
procedure uses this information to determine if a
valid connection is made (cable disconnect,
poor cable quality, etc). In normal Data Mode, if
the box receives 4 seconds of unframed packets
it will restart the box and begin trying to re-
establish a connection with the far end. The dis-
tinction between framed packets and unframed
packets becomes important when we discuss
the Pattern Generator.
Pattern Gen/Det
This part of the Processor generates and
detects the 511/511E patterns. When transmit-
ting 511 patterns, the information is unframed
(because it originates after the framer) and is
intended to be evaluated only by another
Processor. If the units are in Data Mode and the
pattern generator is enabled on one end of the
link, the far end will begin receiving unframed
packets and assume that the line has gone
down. During test modes, we force the pattern
generator to time out before it can cause the link
to be killed.
Loop Control
This part of the Processor is used to control
loop-backs. In a Local Loop, the data is looped
back towards the local DTE (G.703/G.704). In a
Remote Loop, the data is looped back to the
line, but it is also allowed to pass through to the
framer and to the remote DTE (G.703/G.704).
20
Pattern
Gen/Det
Loop
Contr
ol
Loop
Contro
l
Pattern
Gen/Det
Processor
Processor
Framer
Framer
Line
Figure 11: Block Diagram Model 1088
