3040/V35
139001UA
A-3
A
PPENDIX
P
ATTON
E
LECTRONICS
C
O
.
I
NSTALLATION
A
ND
O
PERATIONS
M
ANUAL
Master DTE / Sub-Channel DCE Interface Flow Diagram
Master DTE / Sub-Channel DTE Interface Flow Diagram
Pins P,S TD
Pins R,T RD
Pin C RTS
Pin D CTS
Pin E DSR
Pin F DCD
Pin H DTR
Pins Y,AA TT
Pins V,X RT
Pins U,W ETT
Master RX Clock
Selection Logic
Master TX Clock
Selection Logic
Master Port is a DTE
Switch Control
Channel Port is a DCE
Pins R,T RD
Pins P,S TD
Pin C RTS
Pin D CTS
Pin E DSR
Pin F DCD
Pin H DTR
Pins Y,AA TT
Pins V,X RT
Pins U,W ETT
Master Port is a DTE
Pins R,T RD
Pins P,S TD
Pins P,S TD
Pins R,T RD
Pin C RTS
Pin D CTS
Pin E DSR
Pin F DCD
Pin H DTR
Pin C RTS
Pin D CTS
Pin E DSR
Pin F DCD
Pin H DTR
Switch Control
Buffer
+8v
Pins Y,AA TT
Pins V,X RT
Pins U,W ETT
Pins Y,AA TT
Pins V,X RT
Pins U,W ETT
Clk In
Clk Out
Master RX Clock
Selection Logic
Master TX Clock
Selection Logic
Channel Port is a DTE