40
5
4
3
2
1
HDMI/Audio Blo C k
D
C
B
Not e : P ort A
needs
shieldi ng
grou nd al l
signa l pair
Y
2
C
6
5
H
D
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0
-
R
X
0
P
C
6
6
H
D
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R
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1
N
H
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0
-
R
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1
N
R
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A
1
N
L
I
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_
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1
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1
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1
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1
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-
R
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2
N
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2
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R
A
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3
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6
C
2
3
5
HOTP L
UGA _H
DMI2 0_
5V
H
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B
-
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0
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T
2
A
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6
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P
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P
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2
P
C
1
2
0
6
C
1
2
0
5
H
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B
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C
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K
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B
C
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A
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G
2
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2
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2
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F
H
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C
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S
D
A
D
D
CDB_DA
HDM IB-HPDIN
HOT PLUGB
HOTP LUG B_H DM I2 0_5 V
H OTP LUG B_HDMI 20_ 5V NC
N
C
HDM ID-RX0N
RXD 0N NC
HDM ID-RX0P
R XD0 P
HDM ID-RX1N
RXD 1N I2 S_ OUT _BC K
I2 S_ BCK_OUT
HDM ID-RX1P
R XD1 P I2 S_ OUT _MCK
I2 S _MCK_OUT
HDM ID-RX2N
RXD 2N I2 S_ OUT _WS
I2S_ LRC K_ OUT
HDM ID-RX2P I 2S _D ATA _OUT
AUVAGAUVAG
HDM ID-RX2P
R XD2 P I2 S_ OUT _SD
I2S _DAT A _OUT
HDM ID-CLKN
HDM ID-CLKN
RXDCKN
U5
RX
DCK
P
HDM ID-SDA
U4
HDM ID-SDA
DDCDD_D A
HDM ID-HPDIN
HOTPLU GD GPI O_PM 14
M HL_CAB L E_D ET
HOTP LUGD_HDM I 2 0_ 5V
3D_F L AG
K4
S
P
D
I
F
_
I
N
SPDI F_ OUT
S
P
D
I
F
_
O
U
T
C77
NC/3 3pF
MSD6 A8 2 8/M
SD6 488
U
1
0
0
C
PCMCIA
U
1
0
0
B
A
H
2
8
P
C
M
D
A
T
A
[
0
]
/
C
I
_
D
A
T
A
[
0
]
P
C
M
D
A
T
A
[
1
]
/
C
I
_
D
A
T
A
[
1
]
T
S
1
D
A
T
A
[
0
]
A
J
1
7
P
C
M
D
A
T
A
[
2
]
/
C
I
_
D
A
T
A
[
2
]
T
S
1
D
A
T
A
_
[
1
]
A
K
1
8
P
C
M
D
A
T
A
[
3
]
/
C
I
_
D
A
T
A
[
3
]
T
S
1
D
A
T
A
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[
2
]
P
C
M
D
A
T
A
[
4
]
/
C
I
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D
A
T
A
[
4
]
T
S
1
D
A
T
A
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[
3
]
P
C
M
D
A
T
A
[
5
]
/
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I
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D
A
T
A
[
5
]
T
S
1
D
A
T
A
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[
4
]
P
C
M
D
A
T
A
[
6
]
/
C
I
_
D
A
T
A
[
6
]
T
S
1
D
A
T
A
_
[
5
]
T
S
1
D
A
T
A
_
[
7
]
T
S
_
S
Y
N
C
P
C
M
A
D
R
[
0
]
/
C
I
_
A
[
0
]
T
S
1
C
L
K
T
S
_
V
L
D
P
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M
A
D
R
[
1
]
/
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I
_
A
[
1
]
T
S
1
V
A
L
I
D
T
S
_
D
[
0
:
7
]
P
C
M
A
D
R
[
2
]
/
C
I
_
A
[
2
]
T
S
1
S
Y
N
C
A
J
2
5
P
C
M
A
D
R
[
3
]
/
C
I
_
A
[
3
]
A
K
2
0
P
C
M
A
D
R
[
4
]
/
C
I
_
A
[
4
]
T
S
0
D
A
T
A
_
[
0
]
P
C
M
A
D
R
[
5
]
/
C
I
_
A
[
5
]
T
S
0
D
A
T
A
_
[
1
]
P
C
M
A
D
R
[
6
]
/
C
I
_
A
[
6
]
T
S
0
D
A
T
A
_
[
2
]
P
C
M
A
D
R
[
7
]
/
C
I
_
A
[
7
]
T
S
0
D
A
T
A
_
[
3
]
AG22
PCM ADR [8]/CI_ A[8] T S0D ATA_ [4 ]
AM 22
PCMADR[ 9] /CI _A[9] TS 0DATA _[ 5]
PCMADR[ 1 0]/C I_ A[ 10] T S0D ATA_ [6]
PCMADR[ 1 1]/C I_ A[ 11] T S0D ATA_ [7]
PCMADR[ 1 2]/C I_ A[ 12] T S0C L K
AJ2 2
PCM ADR[ 13]/CI_ A[13 ] TS0 VA LID
A L20
PCMADR[ 1 4]/C I_ A[ 14] T S0SYNC
AJ2 3 AF 15
TS2 _CLK SPI _CSB
AJ2 0 AG 16
T S2 _D0 S PI _M OSI
AH2 0 AH15
T S2_ SYNC S PI_SCK
PCMW EN
PCMCD/CI _CD
PCMRST/CI_R ST
AG21
PCM RE G/CI_CLK
PCMIO WR /CI_ WR
PCMW AIT /CIWACK
AG17
PCM2 _RE SET
PCM2 _ WA IT_N
NAND Flash
NAND-CE1Z NAND-A LE
G 2
NAND-CE 1Z
N AND_ AL E/ EM MC_ IO15 /SD IO_D[1]
NAND-W EZ N AND-W PZ
NAND-WEZ
NAND_ WPZ/ EM MC_ IO17 /SD IO_D[ 2]
NAND-WPZ
NAND_CEZ/ EM M C_IO9
NAND-REZ
NAND_CLE/ EM M C_ IO14 /SD IO _D[ 0]
NAND-A LE N AND-RE Z
NAND-ALE
NAND_REZ /EMM C_I O1 0
NAND-CEZ N AND-WEZ
NAND-CEZ
NAND_WEZ/ EM M CI O16/ SDI O_D [3 ]
NAND-CLE NAND-RBZ
NAND-CL E
NA ND_R BZ/ EM M C_ IO11
NAND-RBZ
NAND_CEZ 1/EM MC_ IO12 /SD IO_CMD
NAND-DQS
NAND_DQS/ EM MC_ IO8 VIF P
DIF P
SDIO _C LK DIFM
1 EM MC_IO1 3/SDI O_C LK VIFM
D IFM
C15 310 0nF
NAND-AD 0
D1
D3
NAND_AD0/ EMM C_IO 6
NAND_ AD1 /EM M C_I O7
NAND_ AD2 /EM M C_I O2
NAND_ AD3 /EM M C_I O1 IF_A GC
IF- AGC
NAND-AD 5
A2
A3
NAND_ AD5/ EMM C_I O 3
A K 8
NAND_ AD6 /EM M C_I O4 TGPI O0
WIFI _CTL
AM 4
TGPI O2/SCK 1
T _SCL
TGPI O3/SDA 1
T _SDA
NAND-AD[ 7: 0]
M SD6 A82 8/MSD 648 8
CHIP_CONFIG[3: 0] {P AD_LED1, P AD_P M_ SPI_DI,P AD_P M_LED0, PAD_P W M_P M}
IC CONF IGUR ATI ON S ELECT ION
+3.3 V _Sta ndb y
R175 4. 7K
Ω
R179 NC/4 .7K
Ω
PM _ LED1
R958
R181 4. 7K
Ω
S PI-SDI
R183 4. 7K
Ω
R959 NC/4 .7K
Ω
PM _ LED0
R960 NC/4 .7K
Ω
PM _P WM
R185 4. 7K
Ω
CHIP _CONFI G[ 3: 0]
{PAD _PM _LED 1, PAD _PM _ SP I_DI , PAD _PM _LED 0, P AD_ PWM_ PM}
Val ue Mo de Descrip tio n
4'b1 0 00 S B51 _ExtS PI 5 1 bo ot fro m S PI
4'b1 0 01 HEMCU_E xt SPI ARM bo ot fro m S PI
4'b1 0 10 HEMCU_ROM _ EM MC ARM b o ot fr o m R OM ; outer st orag e is eMM C
4'b1 0 11 HEMCU_ROM _NAND ARM bo ot fro m R OM; out er st orag e is N AND
4'b1 1 00 DBUS f or test onl y
4'b0 0 00 S B51 _ExtS PI +Aut hentic ati on 5 1 bo ot fro m S PI wi th ARM a uthe ntic ati on
4'b0 0 01 HEMCU_E xt SPI +A ut he ntic ation ARM boo t fr o m SPI wit h au then tica tion
4'b0 0 11 HEMCU_ROM _NAND +Aut h en ticati o n ARM b o ot from R OM wit h au th entic atio n; o ut er st or ag e is NAND
HDMI0-RX0N
RXA0N LINE_IN_0L
VGA_AUL_IN
HDMI0-RX0P
RXA0P LINE_IN_0R
VGA_AUR_IN
C
2
3
4
R
1
7
3
6
C
7
5
1
0
u
F
C
l
o
s
e
t
o
M
S
T
I
C
w
i
t
h
w
i
d
t
h
t
r
a
c
e
F
B
1
1
K
Ω
/
1
0
0
M
H
z
P
C
M
D
A
T
A
[
7
]
/
C
I
_
D
A
T
A
[
7
]
T
S
1
D
A
T
A
_
[
6
]
T
S
_
C
L
K
R
1
7
5
7
N
C
/
1
0
0
Ω
T
S
2
_
V
L
D
S
P
I
_
M
I
S
O
R
8
1
2
Содержание TH-43DX400L
Страница 1: ...11 LED Television Model No TH 43DX400L TH 49DX400L...
Страница 17: ...17...
Страница 19: ...19 Block Diagram System Block Diagram...
Страница 21: ...21 Circuit Block Diagram...
Страница 22: ...22 Power Tree Schematics...
Страница 49: ...48...