Panasonic PT43LCX64 - MMD DIGITAL TUNER, Руководство по обслуживанию, Страница: 84 / 117

VIDEO SIGNAL PATH III BLOCK DIAGRAM (Models: PT-43LCX64 / PT-50LCX65)
VIDEO SIGNAL PATH III BLOCK DIAGRAM
LCD DRIVE C.B.A.
P2001-1
P2001-2
P2001-3
P2001-4
P2001-5
P2001-6
P2001-(7-18)
P2001-19
P2001-20
P2001-21
P2001-22
P2001-23
P2001-24
P2001-25
P2001-26
P2001-27
P2001-28
P2001-29
P2001-30
P2001-31
P2001-32
P2001-33
P2001-34
P2001-35
P2001-36
P2002-36
P2002-2
P2002-1
P2002-3
P2002-4
P2002-5
P2002-6
P2002-(7-18)
P2002-19
P2002-20
P2002-21
P2002-22
P2002-23
P2002-24
P2002-25
P2002-26
P2002-27
P2002-28
P2002-29
P2002-30
P2002-31
P2002-32
P2002-33
P2002-34
P2002-35
P2002-36
P2003-1
P2003-2
P2003-3
P2003-4
P2003-5
P2003-6
P2003-(7-18)
P2003-19
P2003-20
P2003-21
P2003-22
P2003-23
P2003-24
P2003-25
P2003-26
P2003-27
P2003-28
P2003-29
P2003-30
P2003-31
P2003-32
P2003-33
P2003-34
P2003-35
P2003-36
P2501-14
P2501-15
P2501-11
P2501-12
P2501-8
P2501-9
P2501-2
P2501-3
P2501-5
P2501-6
IC2505 (SIGNAL PROCESS FOR LCD PANEL) IC2503 (LVDS RECEIVER)
IC2501
+15.5V
LCD(R)
LCD(G)
LCD(B)
VIDEO SIGNAL(MAIN/SUB)
W4-W6,Y1-Y7
W15-W19,Y16-Y20
A5-A7,B6-B8,
C7,C8
A10-A12,B10-B12,
C10,C11
A15,A16,B14-B16,
C14-C16
30,32-35,
37-39
41-43,45-47,
49,50
1-3,5,51,
53-55
VDD2(+3.3V) +3.3V
+5V
+1.8V
REG.
VDD1(+1.8V)
V1
V2
W3
U1
V13
Y15
Y13
K18
K20
W13
J19
10
9
12
11
16
15
20
19
18
17
E2
D2
E1
H2
29
27
26
C19
1 8
IC2502
+3.3V
REG.
VCC 4 5
13,23,31,40,48,56
H-SYNC
V-SYNC
H-SYNC
R DATA (8BIT) R DATA (10BIT)
G DATA (10BIT)
B DATA (10BIT)
LVDS DATA A(+)
FROM VIDEO II
SIGNAL PATH
BLOCK DIAGRAM
LVDS DATA A(-)
LVDS DATA B(+)
LVDS DATA B(-)
LVDS DATA C(+)
LVDS DATA C(-)
LVDS DATA D(+)
LVDS DATA D(-)
LVDS CLOCK(+)
LVDS CLOCK(-)
G DATA (8BIT)
B DATA (8BIT)
V-SYNC
CLOCK(76 MHz)
SERIAL CLOCK
SERIAL DATA 0
CS(L)
SERIAL CLOCK
FROM
SYSTEM CONTROL
BLOCK DIAGRAM
SERIAL DATA 0
DIR-X <FROM IC2304 (59)>
DIR-Y <FROM IC2304 (50)>
IC2001 CS(L)
IC2002 CS(L)
IC2003 CS(L)
IC2505CS(L)
<FROM IC2304(52)> RESET(L)
<FROM IC2304(57)> CORRECT ON(L)
RESET(L)
CORRECT ON(L)
FRP
DY
DX
ENABLE 4
ENABLE 3
ENABLE 2
ENABLE 1
NRG
CLX
CLY
XFRP
STSQO(R)
XFR(R)
S/H CLOCK(R)
STSQO(G)
XFR(G)
S/H CLOCK(G)
STSQO(B)
XFR(B)
S/H CLOCK(B)
LVDS SERIAL TO
TTL PARALLEL
CONVERTER
PLL
+3.3V
+15.5V
V-REF-H(+7V)
V-REF-L(+5V)
V-REF-H(+7.5V)
V-REF-L(+7V)
IC2001 (SAMPLING HOLD)
96
97
98
99
100
VCC(D)
TP2004
VCC(A)
86-95
52,54,56,58,60,62,
64,66,68,70,72,74
15,26,53,57,61,65,69,73,82
1,50
CONTROL
LOGIC
& DAC LATCH
LEVEL
SHIFTER
(3.3V --> 15.5V)
D/A
CONVERTER INVERTER
AMP
INVERTER
AMP
ON/OFF
SW
ON/OFF
SW
INVERTER
AMP ON/OFF
SW
D/A CONVERTER AMP SW
M19
Y10
V9
W9
Y9
W10
M1
W8
M18
24
23
33
37
36
35
34
27
22
38
25
3
5
4
SERIAL
INTERFACE
SCALE
CONTROL
V1
V2
12
11
10
81
80
79
77
78
13
SCALE
CONTROL
V-REF-H(+7.5V)
V-REF-L(+7V)
V-REF-H(+7.5V)
V-REF-L(+7V)
19
18
39
43
42
41
40
28
44
45
20
21
+3.3V
+15.5V
IC2002 (SAMPLING HOLD)
IC2003 (SAMPLING HOLD)
+3.3V
+15.5V
IC2504 (BUFFER)
V-REF-H(+7V)
V-REF-L(+5V)
V-REF-H(+7V)
V-REF-L(+5V)
D20,E19,E20,F19,F20,
G19,G20,H19,H20,J18
2
3
7
5
4
6
18
17
13
15
16
14
B18
B20
B19
XDIR-X <FROM IC2304 (60)>
Q2003
TP2005
TP2006
TP2901
96
97
98
99
100
VCC(D)
VCC(A)
86-95
52,54,56,58,60,62,
64,66,68,70,72,74
15,26,53,57,61,65,69,73,82
1,50
CONTROL
LOGIC
& DAC LATCH
LEVEL
SHIFTER
(3.3V --> 15.5V)
D/A
CONVERTER
D/A CONVERTER AMP SW
24
23
33
37
36
35
34
27
22
38
25
3
5
4
SERIAL
INTERFACE
SCALE
CONTROL
V1
V2
LCDCOM
LCDCOM
LCDCOM
12
11
10
81
80
79
77
78
13
SCALE
CONTROL
19
18
39
43
42
41
40
28
17
44
45
20
21
96
97
98
99
100
VCC(D)
VCC(A)
86-95
52,54,56,58,60,62,
64,66,68,70,72,74
15,26,53,57,61,65,69,73,82
1,50
CONTROL
LOGIC
& DAC LATCH
LEVEL
SHIFTER
(3.3V --> 15.5V)
D/A
CONVERTER
D/A CONVERTER AMP SW
24
23
33
37
36
35
34
27
22
38
25
3
5
4
SERIAL
INTERFACE
SCALE
CONTROL
V1
V2
12
11
10
81
80
79
77
78
13
SCALE
CONTROL
19
18
39
43
42
41
40
28
44
45
20
21
NON UNIFORMITY COLOR COMPENSATION
GAMMA CORRECTION
WHITE BALANCE CONTROL
TIMING GENERATOR FOR PANEL DRIVE
6
6
6
TP2001
(IC2001 PIN52 LINE)
TP2003
(IC2003 PIN52 LINE)
TP2002
(IC2002 PIN74 LINE)
H4,H5,ETC
D7,D8,ETC
PT-43LCX64/PT-50LCX64