PGA26E07BA-SWEVB008 Ver. 1.2
12
- Switching loss test circuit
Inductor L1 is connected between VPN and LX, same as low side dV/dT test. The V
DS
connection is between
QA Drain and Source2 pin. The V
GS
is not monitored to avoid shorting the Source1 and Source2 pin of the
GaN device QA. The voltage across RS is measured by connecting an SMA cable to a 50 ohm terminated
channel of the oscilloscope. Loss Test procedure is explained further in page 17.
- Dead time circuit
Dead time circuit is required to ensure both GaN transistor QA and QB do not turn ON at the same time. Figure
8 shows a simple example of dead time adjustment circuit. The phasing of inverting and non-inverting outputs
can be fine-tuned by adjusting resistor R1. XOR1 and XOR4 logic gate produce compliment of the input signal.
XOR2 and XOR3 logic gate output the signals with the delay time. The delay times can be set by adjusting the
passive components R2 and R3.
Figure 8: Dead Time Circuit
Figure 7: Low Side Loss Test circuit
Содержание PGA26E07BA-SWEVB008
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