Panasonic Panafax UF-5300, Руководство по обслуживанию

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6.2.14 LAN Control Circuit (Option)
LAN Controller
1. LAN Controller (IC1)
This conforms to IEEE 802.3 Ethernet Controller. The CPU (SC PCB) bus is directly connected and the
data interrupt is controlled by pLANINT. The 25 MHz clock is supplied by X1. The LAN Controller for
the system timing clock divides the frequency provided from X1. The clock signal is also supplied for
the Manchester encoding/decoding circuit for data conversion.
The LAN Controller is a mixed signal Analog/Digital device that implements the MAC and PHY portion
of the CSMA/CD protocol at 10 and 100Mbps.
The LAN controller contains a built in 8 KByte RAM for transmission and reception buffer.
2. EEPROM (IC2)
This memory stores the configuration registers and MAC (Media Access Control) address for the LAN
controller. Data is transferred to LAN controller (serial transfer) when the power is turned "On". The
MAC address for the LAN controller represents the location on the LAN.
3. Ethernet Interface (RJ45 Connector)
Provides the 10Base-T/100Base-TX Ethernet interface.
Two LED (LINK and Activity) and Transformer module are in the RJ45 Connector.
a. LINK LED
The LINK LED normally illuminates when the LAN cable is connected and when a link pulse is
detected. Consequently, LED can be used to determine whether the 10Base-T/100Base-TX cable
has become disconnected (RX side).
b. Activity LED
This LED illuminates when reception data is present on the LAN. (The LED also illuminates when
reception data for other devices is present.)
CPU
V850E/MA1
(IC1)
SHINE
DZAC000273
(IC3)
FROM 4MB
Program
(IC9)
FROM 8MB
Image Memory
(IC10)
MN86075
(IC30)
MODEM
MMD5020
(IC22)
DAA
Si3056,
Si3019
(IC23, 24)
D-BUS
Laser Printer CCD PCB
Line
Line
Memory
Page
Memory
ECM
Buffer
S-DRAM 8MB
(IC7)
LAN
Controller
(IC1)
RJ45
LINK
RX
INTERNET
(10Base-T/100Base-TX)
LAN PCB
EEP
ROM
(IC2)
25MHz
X1
(1)
(2)