3 Block Diagrams
NV-GS80EG/EF/E/EP/EB/EK/EE, NV-GS85GC/EE, NV-GS88GK
CCD DRIVE BLOCK DIAGRAM
CCD DRIVE BLOCK DIAGRAM
7
10
4
9
13
12
3
2
1
CCD
IMAGE
SENSOR
IC601 (CCD)
FP31
4
FP31
V1
V2
V3
V4
RESET
H1
H2
SUB
3
FP301
14
FP31
5
FP31
6
FP31
13
FP31
12
FP31
10
LEVEL
CHANGE
LEVEL
CHANGE
LEVEL
CHANGE
LEVEL
CHANGE
LEVEL
CHANGE
LEVEL
CHANGE
LEVEL
CHANGE
DRIVE
DRIVE
5
7
8
9
14
13
12
10
37
53
44
39
38
45
40
48
31
32
35
3
17
18
1
IC303 (CCD V-DRIVE)
IC302 (CAMERA SIGNAL PROCESS/TIMING GENERATOR)
Q601
BUFFER
CCD P.C.B.
MAIN P.C.B
V1 PULSE
CHARGE PULSE 1
V2 PULSE
V3 PULSE
CHARGE PULSE 2
V4 PULSE
SUB CONTROL PULSE
H1 PULSE
H2 PULSE
RESET PULSE
1
3
2
CDS
PGA
10BIT A/D
CONVERTER
SERIAL INTERFACE
REC VIDEO(CAMERA) SIGNAL
64
24
29
28
FCK
VD
HD
CAMERA DATA (0-9)
CG/AFE SERIAL CLOCK
CG/AFE SERIAL DATA
CAMERA AFE CS (L)
FCK (18.0MHz)
CAM HD
CAM VD
23
XOUT
XIN
12MHz CLOCK
X301
36MHz
OSC
TO/FROM VIDEO SIGNAL PROCESS I
BLOCK DIAGRAM
CG CS (L)
FP31
1
CAMERA DATA (10 BIT)
6
9
22
17
12MHz CLOCK
11
16
2.85 Vp-p
1 V
5 ms
V1
9