NOTE:
FOR SCHEMATIC DIAGRAM AND CIRCUIT BOARD LAYOUT NOTES,
REFER TO BEGINNING OF SCHEMATIC SECTION.
NOTE:
PARTS MARKED "PT" ARE NOT USED.
NOTE: For placing a purchase order of the parts,
be sure to use the part number listed in the parts list.
Do not use the part number on this diagram.
LSJB8361
NV-GS80EG/EF/E/EP/EB/EK/EE, NV-GS85GC/EE, NV-GS88GK
MAIN VI SCHEMATIC DIAGRAM (2/2)
MAIN VI SCHEMATIC DIAGRAM (2/2)
CLK27A
237
REQR
316
TP3003
ALCPWM
263
CTL_TDO
167
DUO_TDO
327
TP3002
TP3001
R3010
10K
C3024
220P[JC]
R3009
10K
C3025
1[KB]
R3011
3.6[D]
R3012
3.6[D]
R3013
3.6[D]
R3014
3.6[D]
TPA+
323
TPB+
325
TPB-
326
TPA-
324
C3023
0.1[KB]
L3013
J0JBC0000027
R3008
12K[D]
L3015
10U
HID1
322
R3006
1M
C3021
33P
C3020
22P
X3001
H0J245500064
R3007
100
C3016 0.1[KB]
C3027
0.1[KB]
C3034
0.1[KB]
C3032
0.1[KB]
C3031
0.1[KB]
C3029
0.1[KB]
C3028
0.1[KB]
R3034
10K[D]
R3035
10K[D]
DUO_YOUT
287
DUO_COUT
286
R3032
10K[D]
R3033
12K[D]
C3035
0.01[KB]
C3033
0.01[KB]
R3031
15K
R3030
10K
C3030
0.01[KB]
IRISOPEN
262
IRISCLOSE
261
HOST_REQ
182
HOST_ACK
183
DUO_INT3
229
DUO_INT2
228
DUO_INT0
226
DUO_INT1
227
R3041
PT
ACKR
317
INTSEG
309
READH
310
VAL
311
ADDA[0]
312
ADDA[1]
313
ADDA[2]
314
ADDA[3]
315
DBR[0]
318
DBR[1]
319
DBR[2]
320
DBR[3]
321
C3037
1[KB]
R3015
47K
R3016
47K
R3017
47K
R3018
47K
R3019
47K
C3038
0.01[KB]
C3022
0.01[KB]
R3029
0
BCK
289
SDI
292
LRCK
291
MCK
290
SDO0
288
C3008
22/4V
C3009
0.01[KB]
C3036
0.01[KB]
0.01[KB]
C3007
0.1[KB]
0.1[KB]
C3026
0.1[KB]
C3017
C3018
PT
2V_TMS
166
2V_TCK
165
TP3026
TP3027
TP3028
TP3029
TP3030
R3040
0
R3079
0
R3080
0
R3081
0
R3082
0
R3077
PT
R3078
PT
R3087
47K
R3085
0
83
R3088
47K
R3084
47K
L3016
J0JBC0000027
DUO213
303
DUO201
293
DUO215
305
DUO210
300
DUO212
302
DUO209
299
DUO211
301
DUO206
296
DUO205
295
DUO214
304
DUO202
294
DUO207
297
DUO208
298
INF
307
FRP
306
SSP
308
10[KB]
C3006
C3015 10[KB]
LYCIO[1]
283
LYCIO[4]
280
LYCIO[3]
281
LYCIO[2]
282
LYCIO[0]
284
LYCIO[6]
278
CLK27C
285
LYCIO[7]
277
LYCIO[5]
279
TP3034
TP3035
TP3036
0.01[KB]
C3005
IC3001
C1AB00002028
A1
TMS
D4
TCK
B1
TDI
F6
VDD18
C2
TDO
F5
VDD18
C1
XDUO_CS
D3
E4
D2
D1
G7
VSS
F4
E3
E2
E1
G6
VSS
G5
VDD15
F3
F2
F1
G4
H6
VSS
G3
G1
G2
H5
VDD18
H4
H3
ALE
H1
XWEH
H2
XWEL
J6
VDD18
J4
XRE
J3
XREAD
Y
J1
XRST_ARM
J2
VDD15
J5
VSS
K6
VCO_A
VDD25
K5
VCO_A
VDD25
K1
FSLPFI
K3
VCO_A
VSS
K2
VCO_A
VSS
K4
PLL_A
VDD25
L5
PLL_A
VDD25
L1
PLL_A
VSS
L6
PLL_A
VSS
L2
VSS
L3
FCK45
L4
CAMHD
M1
CAMVD
M4
M2
M5
VDD18_30
M3
N1
N3
N2
N4
P1
P2
P3
N5
VDD18_30
P4
FCA
R1
FCB
R2
F2C
R3
ZA
COMP
M6
VSS
P5
VDD15
T1
ZBCOMP
T2
ZCCOMP
T3
ZDCOMP
R4
SIG
U1
ALCPWM
N6
VDD18_30
U2
IRISCLOSE
T4
IRSOPEN
U3
HOST_REQ
V1
HOST_A
CK
R5
VDD18_30
V2
DUO_INT3
P6
VSS
W1
DUO_INT2
U4
DUO_INT1
V3
DUO_INT0
W2
VSS
T5
VDD15
Y1
VSS
R6
VSS
Y2
VDD18_30
AA1
VDD18_30
W3
SD_VDD15
V4
SD_VDD15
AA2
SD_VSS
U5
SD_VSS
Y3
SD_VDD25
T6
VDD18
AA3
SCLK54I
W4
VDD18
V5
CLKSEL2
Y4
CLK27B
U6
CLKSEL0
AA4
CLK27A
T7
CLKSEL1
W5
CLK135
Y5
SD_VDD25
AA5
SD_VSS
V6
SD_VDD15
U7
VSS
W6
VDD15
Y6
TESTMD[0]
AA6
TESTMD[1]
V7
TESTMD[2]
T8
SD_VDD15
W7
SD_VSS
AA7
SD_VDD25
Y7
TESTMD[3]
U8
TESTMD[4]
V8
TESTMD[5]
W8
VSS
AA8
VDD18
Y8
VSS(NC)
T9
VDD18
U9
S400
V9
BIAS2K
Y9
VSS
AA9
CLK24I
W9
VDD25
T10
VSS(NC)
U10
VSS(NC)
AA10
CLK24O
W10
SD_VDD25
V10
SD_VSS
Y10
SD_VDD15
U11
VDD15
AA11
1394_AVSS
T11
1394_AVDD15
W11
1394_AVSS
V11
R[1]
Y11
VSS(NC)
AA12
R[0]
V12
1394_AVDD30
U12
VSS(NC)
Y12
1394_AVSS
W12
1394_AVSS
AA13
T12
VSS(NC)
W13
VSS(NC)
Y13
V13
VSS(NC)
AA14
Y14
W14
TPBIAS
U13
1394_AVDD30
AA15
1394_AVDD15
V14
VDD15
Y15
XRST
W15
SSP
T13
VDD18
AA16
HID
U14
VDD18
Y16
W16
V15
AA17
T14
VSS
Y17
ACKR
V16
REQR
AA18
W17
U15
VSS
Y18
T15
VDD15
AA19
V17
VAL
W18
READH
Y19
INTSEG
U16
VDD18
AA20
U17
VDD18
W19
Y20
AA21
V18
Y21
AID
AT
2
T16
W20
T17
SDCLK
W21
VSS
V19
VDD32
U18
VSS
V20
D
A
C_A
VSS
V21
CREF
R16
CVBS
T18
U19
D
A
C_A
VDD25
U20
D
A
C_A
VSS
U21
YREF
R17
YVBS
R18
T19
D
A
C_A
VDD25
T20
D
A
C_A
VDD25
T21
D
A
C_A
VSS
P16
D
A
C_A
VSS
P17
LCDBVBS
R19
R21
D
A
C_A
VDD25
R20
D
A
C_A
VSS
P18
LCDREF
N16
LCDGVBS
P19
P21
D
A
C_A
VDD25
P20
D
A
C_A
VDD25
N17
D
A
C_A
VSS
N18
D
A
C_A
VSS
N19
LCDR
VBS
N21
N20
D
A
C_A
VDD25
M16
VSS
M17
VDD18
M18
B
US_MODE
M21
VDD18
M19
VSS
M20
L17
L16
VDD15
L21
K17
L20
L19
L18
K21
K18
CLK27X
K20
YCIO[7]
K16
YCIO[6]
K19
YCIO[5]
J21
YCI0[4]
J19
VSS
J20
YCI0[3]
J18
YCIO[2]
J16
YCI0[1]
H18
YCI0[0]
H21
CLK27D
H20
H19
J17
H16
H17
G21
G20
G19
G18
G17
F21
F20
VSS
F18
VDD18
D19
E18
F17
INF
D21
FRP
E21
VDD18
E20
F19
C20
C21
D20
VDD15
E19
B21
G16
E17
B20
CLK27C
A21
VSS
C19
ADECD
AT
D18
VSS
A20
F16
B19 VSS(NC)
E16 CMD
A19 VSS(NC)
C18 SD_VDD32
D17 VDD15
B18 CLK48O
A18 CLK48I
F15 VSS(NC)
D16 VSS(NC)
C17 VSS(NC)
B17 VDD25
A17 VSS
E15 VSS(NC)
D15 VSS(NC)
C16 VSS(NC)
B16
A16
F14 VSS
E14 USB_VDD32
C15 USB_VDD32
A15 VDD30
B15 CAMLENSDTO
D14 CAMLENSCLK
F13 CAMLENSCS
C14 CAMCGAFEDTO
A14 VDD30
B14 CAMCGAFECLK
E13 CAMCGCS
D13 CAMAFECS
C13 VSS
A13 OSDVR
B13 OSDVG
F12 OSDVB
E12 OSDBLKA
D12 VSS
A12 VDD15
C12 OSDBLKB
B12 FAD_VDD15
E11 FAD_VSS
F11 FAD_VDD32
A11 OSDHD
E10 OSDVD
B11 LCDVBLK
C11 LCDHD
D11 VSS
A10 LCDPOL
D10 VDD30
B10 CLK45M_ZB
F10 AFDRVD
C10 LINPWM
A9 OSDCLK
C9 FSLPFO
B9 DTCLK
D9 DVM
A8 FAD_VDD32
B8 FAD_VSS
C8 FAD_VDD15
E9 VDD30
D8 VDD18
A7 TRACECLK
B7 TRACESYNC
C7 TRACEPKT[0]
F9 TRACEPKT[1]
E8 VDD18
A6 VDD15
B6 VSS
C6 SD_VDD15
D7 SD_VSS
A5 SD_VDD25
F8 TRACEPKT[2]
B5 TRACEPKT[3]
D6 TRACEPKT[4]
C5 TRACEPKT[5]
A4 TRACEPKT[6]
E7 TRACEPKT[7]
B4 PIPESTAT[0]
F7 PIPESTAT[1]
A3 PIPESTAT[2]
D5 A15
C4 VSS
B3 SD_VDD25
E6 SD_VSS
A2 SD_VDD15
E5 VSS
C3 RTCK
B2 XTRST
NC
NC
NC
ADM[0]
ADM[1]
ADM[2]
ADM[3]
ADM[4]
ADM[5]
ADM[6]
ADM[7]
ADM[8]
ADM[9]
ADM[10]
ADM[11]
ADM[12]
ADM[13]
ADM[14]
ADM[15]
ADIN[0]
ADIN[1]
ADIN[2]
ADIN[3]
ADIN[4]
ADIN[5]
ADIN[6]
ADIN[7]
ADIN[8]
ADIN[9]
DBR[0]
DBR[1]
DBR[2]
DBR[3]
ADDA[0]
ADDA[1]
ADDA[2]
ADDA[3]
DUO_INT0
DUO_INT1
DUO_INT2
DUO_INT3
DUO_INT0
DUO_INT1
DUO_INT2
DUO_INT3
REQR
ACKR
VAL
READH
INTSEG
INTSEG
READH
VAL
ADDA[0]
ADDA[1]
ADDA[2]
ADDA[3]
REQR
ACKR
DBR[0]
DBR[1]
DBR[2]
DBR[3]
SDD
AT
A3
SDD
AT
A2
1
0
ADD
A[0]
ADD
A[1]
ADD
A[2]
ADD
A[3]
INTSEG
REQR
DUO201
DUO202
DUO205
DUO206
DUO207
DUO214
DUO213
DUO212
DUO211
DUO210
DUO209
DUO208
DUO215
DUO215
DUO214
DUO213
DUO212
DUO211
DUO210
DUO209
DUO207
DUO208
DUO206
DUO205
DUO201
DUO202
[DUO]
[1608]
[1608]
[2012]
[24.576MHz]
[1608]
[1608]
CAMERA DIGITAL SIGNAL
PROCESS/SHUFFLING
PB AUDIO SIGNAL
REC VIDEO SIGNAL
REC AUDIO SIGNAL
PB VIDEO SIGNAL
5
4
9
6
7
8
D/A
CONVERTER
D/A
CONVERTER
DRAM
IEEE1394
INTERFACE
DIS CONTROL/ZOOM CONTROL/EFECT CONTROL/JPEG/GUI
MICROCONTROLLER INTERFACE
DV
INTERFACE
USB
INTERFACE
SD
INTERFACE
DRAM
D/A
CONVERTER
D/A
CONVERTER
D/A
CONVERTER
DIGITAL SIGNAL PROCESS
CAMERA SIGNAL
PROCESS
AUDIO
DIGITAL
SIGNAL
PROCESS
TO M XI(A-1)
TO M XI(A-1)
TO M XI(A-1)
TO M XI(A-1)
TO M XI(A-1)
TO M XI(A-1)
TO M XI(A-1)
TO M XI(A-1)
TO M XI(A-1)
TO M VIII(B-6)
TO M VIII(B-6)
TO M VIII(A-1)
TO M VIII(A-1)
TO M VIII(A-1)
TO M VIII(A-1)
TO M X(C-4)
TO M VIII(A-1)
TO M X(C-4)
TO M X(C-4)
TO M X(C-4)
TO M X(B-4)
TO M X(B-4)
TO M X(C-4)
TO M X(B-4)
TO M X(C-4)
TO M X(C-4)
TO M X(B-4)
TO M X(B-4)
TO M X(B-4)
TO M X(C-4)
TO M X(C-4)
TO M X (B-4)
TO M VII(D-1)
TO M VII(D-1)
TO M VII(D-1)
TO M VII(D-1)
TO M VII(D-1)
TO M VII(D-1)
TO M VII(D-1)
TO M VII(D-1)
TO M VII(D-1)
TO M VII(D-1)
TO M VII(D-1)
TO M VII(D-1)
TO M VII(D-1)
TO M VII(D-1)
TO M XII(B-1)
TO M XII(B-1)
TO M XII(B-1)
TO M XII(B-1)
TO M III(C-1),
VII(D-1),X(B-4)
TO M II(A-13)
TO M II(A-13)
TO M II(A-13)
TO M II(A-13)
TO M I(A-4)
TO M VII(A-1)
TO M I(A-3)
TO M I(A-3)
TO M V(D-1)
TO M V(D-1)
TO M V(D-1)
TO M II(B-1)
TO M II(B-1)
85GC/EE, 88GK
LINK TO VOLTAGE CHART
LINK TO I/O CHART
30
