PV-GS80P/PV-GS80PC/PV-GS83P/PV-GS85P/PV-GS85PC
I/O CHART OF IC3201
IC5001 IC- DETAIL BLOCK DIAGRAM
I/O CHART OF IC3201
IC5001 IC-DETAIL BLOCK DIAGRAM
Pin No.
Pin No.
I/O
Signal Name
Description
I/O
Signal Name
Description
-
DVSS
Ground
A1
-
VRH
V-ref : high
B1
-
V-ref : low
VRL
B2
I
AVD12 (ADC1)
+1.8V
C1
ADTEST
Test pin
-
C2
AVS12 (ADC1)
-
Ground
C3
I
AVD14 (AMP1)
+1.8V
D1
AVS14 (AMP1)
-
Ground
D2
I
PBIN
PB data input (+)
D3
I
AVD15 (ADC2)
+1.8V
D4
I
ATFIN
ATF input
E1
AVS15 (ADC2)
-
Ground
E2
I
AVD13 (ADC1/2)
+1.8V
E3
AVS13 (ADC1/2)
-
Ground
E4
I
AVD16 (VREF)
+1.8V
F1
-
VCORP
VCO reference resister
F2
AVS16 (VREF)
-
Ground
F3
AVS22 (DAC2/3)
-
Ground
G1
O
OSO
Offset output
G2
V-ref3
-
VREF3
F4
V-ref2
VREF2
-
G3
I
AVD22 (DAC2/3)
+1.8V
H1
O
ATF0
ATF output
H2
V-ref1
-
VREF1
G4
FPORP
O
Frequency Phase out (+)
J1
AVS21 (DAC1)
-
Ground
J2
I
AVD21 (DAC1)
+1.8V
H3
-
FRP
(Not used)
K1
I
VCOIN
VCO input
L1
AVS11 (VCO)
-
Ground
L2
I
AVD11 (VCO)
+1.8V
K2
I
DVDD25
+2.5V
L3
O
AGCCTL
AGC control
K3
O
RECCUR
Rec current control
J3
CAPERR
Capstan error
O
L4
CYLERR
Cylinder error
O
K4
CAPRSF
Capstan motor Reverse(H)/Stop(M)/Forward(L)
O
J4
-
DVSS
Ground
H4
I
TRST
Reset : low
L5
I
TMS
Test mode of JTAG
K5
I
TDI
Test data out of JTAG
J5
O
TDO
Test data In of JTAG
H5
I
TCK
Test clock of JTAG
L6
O
HID1
Head switch pulse 1
K6
O
HID2
Head switch pulse 2
J6
O
SPA
Sample pulse for ATF
L7
-
DVSS
Ground
K7
O
RECI
Rec on/off control
H6
I
EQHLD
Equalizer hold
J7
O
HSE
Rec data
L8
O
RECCLK
Rec clock
K8
I
DVDD18
+1.8V
H7
O
RECCTL
Rec control
L9
O
PBH
PB mode : high
K9
I
CYLFG
Cylinder FG head
J8
O
DriveCLK
Drive clock
L10
-
DVSS
Ground
L11
I
CYLPG
Cylinder PG head
K11
-
ADM[0]
(Not used)
K10
-
ADM[1]
(Not used)
J11
I/O ADM[2]
Address/data 2
J10
I
ADD18
+1.8V
J9
I/O ADM[3]
Address/data 3
H11
I/O ADM[4]
Address/data 4
H10
I/O ADM[5]
Address/data 5
H9
-
DVSS
Ground
H8
I/O ADM[6]
Address/data 6
G11
I/O ADM[7]
Address/data 7
G10
I/O ADM[8]
Address/data 8
G9
I
DVDD18
+1.8V
G8
I/O ADM[9]
Address/data 9
F11
I/O ADM[10]
Address/data 10
F10
I/O ADM[11]
Address/data 11
F9
I/O ADM[12]
Address/data 12
E11
-
DVSS
Ground
E10
I/O ADM[13]
Address/data 13
F8
I/O ADM[14]
Address/data 14
E9
I/O ADM[15]
Address/data 15
D11
I
AS
Address strobe
D10
I
DVDD18
+1.8V
E8
I
XRE
Read enable
C11
XWEL
I
Write enable
C10
XWEH
I
Write enable
D9
I
CLK27A
27MHz clock
B11
DVSS
-
Ground
A11
DVR[0]
I/O
Digital Rec/PB data (0)
A10
I/O DVR[1]
Digital Rec/PB data (1)
B10
I/O DVR[2]
Digital Rec/PB data (2)
A9
I/O DVR[3]
Digital Rec/PB data (3)
B9
I
DVDD18
+1.8V
C9
O
REQR
Request of R10
A8
I
ACKR
Acknowledge for R10
B8
-
TSTCKI
(Not used)
C8
-
DVSS
Ground
D8
-
TSTDT[0]
(Not used)
A7
-
TSTDT[1]
(Not used)
B7
-
TSTDT[2]
(Not used)
C7
I
DVDD18
+1.8V
D7
-
TSTDT[3]
(Not used)
A6
-
TSTDT[4]
(Not used)
B6
-
TSTDT[5]
(Not used)
C6
-
TSTDT[6]
(Not used)
A5
-
DVSS
Ground
B5
-
TSTDT[7]
(Not used)
D6
-
TSTDT[8]
(Not used)
C5
-
TSTDT[9]
(Not used)
A4
I
VPD
+1.8V
B4
I
DVDD18
+1.8V
D5
I
XRST
Reset : low
A3
-
TSTMD
(Not used)
B3
-
CS
(Not used)
C4
-
GESW
(Not used)
A2
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
23
24
25
26
27
28
29
30
31
32
33
11
10
9
8
7
6
5
4
3
2
1
VCC
(+3V)
GND
VCC
(+1.8V)
GND
GND
GND
VCC
(+5V)
CH2
CH1
AGC
DET
LOGIC
CH2
CH1
AGC
LOGIC
DRIVE
GCA
ENVE
DET
LPF
AMP
33
