8. CIRCUIT OPERATION
8.1. Control-System Circuit
8.1.1. CPU Peripherals
- CPU (System clock: 12.288 MHz)......IC507
Data bus: 16bit, Address bus: 23bit
- Flash ROM (8Mbit)......IC504
Flash memory consists of two areas: boot space and
administration space.
administration program can be rewritten through downloading.
- SRAM (2Mbit)......IC503, IC506
Used for the data buffer for CPU work area, and PT
communication.
- Dual port RAM (128byte)......Uses a part of the functions of IC7.
Used for the buffer for the communications with MPR.
- Reset
On boot-up, ASIC reset release is carried out by EC_nRST from
MPR. After the ASIC reset release, CPU reset is released by the
soft reset release from MPR; then, LPR program starts up.
- Operation in instantaneous interruption
When instantaneous power interruption is 300msec or less, reset
operation is not carried out because the voltage is retained by the
capacitor in the power supply. However for the purpose of
reducing the power consumption during instantaneous
interruption, if it is detected (nHALT=L), power down mode is
established and CPU itself goes into sleep mode. CPU sleep is
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