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8.2.2 Downlink I and Q
Figure 3:
Functional structure of the baseband Downlink path
450-0803
8.2.3 Power amplifier Ramp
The PA Ramp is formed by 2 D/As, The first, a 5 bit D/A defines the ramp shape, and the second an 8 bit D/A
defines the maximum level.
The Ramp Shape defined by 64 steps, the shape can be defined differently for rising and falling ramps. Typically a
raised cosine shape will be used as a starting basis of the ramp shape.
Figure 4:
Example for the PA ramp
450-0804
The raised cosine shape will be modified to compensate for RF circuit characteristics.
The ramp time is selectable between each step being 1/16 of a bit and each step being 1/8 of a bit giving a
maximum ramp time of either 14.77uS or 29.53uS.
An 8 bit value is used to program the ramp output level.
Issue 1
Section 8
MCUK971001G8
Revision 0
8 - 2
Technical Guide
VEGA
Offset
Offset
Offset
Offset
Calibration
Calibration
Antialiasing
Filter
Filter
Filter
Filter
Filter
Filter
Sigma_Delta
Sigma_Delta
Modulator
Modulator
SINC
SINC
FIR
FIR
Register
Register
SUB
SUB
To baseband
serial
interface
fs3=270.8 Khz
fs2=1.08 Mhz
fs1=6.5 Mhz
Antialiasing
DLIP
DLIN
DLQP
DLQN
63
Step
0.00
5.00
10.00
15.00
20.00
25.00
30.00
35.00
0
3
6
9
12
15
18
21
24
27
30
33
36
39
42
45
48
51
54
57
60
5
b
itD/A
V
alue
Ramp Up
0.00
5.00
10.00
15.00
20.00
25.00
30.00
35.00
0
3
6
9
12
15
18
21
24
27
30
33
36
39
42
45
48
51
54
57
60
5
b
itD/A
V
alue
63
Step
Ramp Down