Section 150-619-100
Revision 01
Page 4
4. ABOUT THE HLU-619
4.01 The HiGain-2 system uses PairGain’s 2-Bit
1-Quartenary (2B1Q) VHDSL transceiver systems to
establish one full duplex 1.568 kbps data channel
between the HLU-619 and a remotely mounted
HRU-612 HiGain-2 Remote Unit.
4.02 A block diagram of the HLU-619 is shown in
Figure 2. The HiGain-2 HLU-619 receives a 1.544
Mbps DS1 data stream from the DSX-1 digital cross
connect interface. The HLU-619 contains a DSX-1
frame synchronizer controlled by an 8-bit
microprocessor, which determines the type of
framing on the DSX-1 stream and synchronizes to it.
The HLU-619 recognizes Super Frame (SF) or
Extended Super Frame (ESF) framing. When the
data is unframed, the HLU-619 arbitrarily defines a
frame bit.
4.03 The HLU-619 contains a multiplexer that
generates a 1.568 kbps data stream. The data
stream contains VHDSL frames, which are 9,408
bits (6 milliseconds) in length. The VHDSL frames
contain a 14-bit Frame Sync Word (FSW), 6-bit
Cyclic Redundancy Check (CRC), 21-bit operations
channel and DSX-1 payload.
4.04 The formatted VHDSL channel is passed to
the VHDSL transceiver, which converts it to a 2B1Q
format on the VHDSL line. The 2B1Q line code is
designed to operate in a full-duplex mode on one
unconditioned pair. The transceiver echo canceler
and adaptive equalizer receive the signal from the
remote end in the presence of impairments and
noise on the copper pair.
4.05 The received VHDSL channel is processed by
the transceiver and then passed on to the HLU-619
demultiplexer module. The demultiplexer provides
frame synchronization for the VHDSL channel. The
demultiplexer and VHDSL transceiver work under
control of the HLU-619 microprocessor and
compensate for data inversions caused by tip-ring
reversals. By synchronizing to the Frame Sync
Word (FSW) of the VHDSL channel, the
demultiplexer can reconstruct the original 1.544
Mbps DS1 stream from the VHDSL channel. The
CRC fields on the VHDSL streams allow the HLU-
619 to determine if errors are present on the channel
due to excessive impairments on the VHDSL pairs
or excessive impulse or crosstalk noise.
4.06
The demultiplexer removes data link
messages from the VHDSL channel and passes
them to the microprocessor. This mechanism allows
operations messages and status to be exchanged
between the HLU-619 and the HRU-612 remote unit.
4.07 The reconstructed VHDSL data channel is
buffered in a first-in-first-out buffer (FIFO) within the
demultiplexer. A frequency synthesizer, in
conjunction with the FIFO, regulates the output bit
rate and reconstructs the DSX-1 clock at the exact
rate received from the remote end. The HiGain-2
system operates at T1 rates of 1.544 Mbps with up
to
±
200 bps of offset.
4.1 DSX-1 INTERFACE DRIVER
4.11 This driver converts the input data to an
Alternate Mark Inversion (AMI) or Binary Eight Zero
Substitution (B8ZS) format. The DSX-1 equalizer is
programmable to five different lengths, as
determined by the distance between the HLU-619
and the DSX-1 interface. This provides CB-119
specification compliant pulses at the DSX-1 interface
over a range of 0 to 655 feet of ABAM-specification
cable.
