Optical Systems Design OSD2512, Руководство пользователя

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OPTICAL SYSTEMS DESIGN
DOC ID: 10118101
OSD2512 OPERATOR MANUAL
PAGE 176
Top: Clock selector is locked to Time over packets, e.g. PTP (See next).
Clock Source
The clock source locked to when clock selector is in locked state.
LOL
Clock selector has raised the Los Of Lock alarm.
DHOLD
Clock selector has not yet calculated the holdover frequency offset to local oscillator. This
becomes active for about 10 s. when a new clock source is selected
STATION CLOCK CONFIGURATION
The Synce module may have a Station clock input and/or a Station clock output.
Clock input frequency
If supported by the Synce HW, the station clock input frequency can be configured, the
possible frequencies are:
1,544 MHz, 2,048 MHz or 10 MHz
Clock Output frequency
If supported by the Synce HW, the station clock output frequency can be configured, the
possible frequencies are:
1,544 MHz, 2,048 MHz or 10 MHz
SYNCE PORTS
For each possible port on switch.
Port
The port number to configure.
SSM Enable
Enable and disable of SSM functionality on this port.
Tx SSM
Monitoring of the transmitted SSM QL on this port. Transmitted QL should be the Quality
Level of the clock generated by this node. This means the QL of the clock source this node is
locked to
Rx SSM
Monitoring of the received SSM QL on this port. If link is down on port, QL_LINK is
indicated. If no SSM is received, QL_FAIL is indicated
1000BaseT Mode
If PHY is in 1000BaseT Mode then this is monitoring the master/slave mode. In order to
receive clock on a port, it has to be in slave mode. In order to transmit clock on a port, it has to
be in master mode