NCP1219PRINTGEVB
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6
winding. Care must be taken not to exceed the thermal
capability of the IC. The power dissipated during DSS mode
is approximated by Equation 20.
P
DSS
+
I
CC3
@
V
HV
(eq. 20)
where V
HV
is the HV pin voltage, and I
CC3
is the controller
supply current during normal switching operation. I
CC3
has
a component that is dependant on the gate charge of Q5, as
shown in Equation 21,
I
CC3
+
I
CC2
)
Q
g(tot)
@
f
SW
(eq. 21)
where Q
g(tot)
is the total gate charge of Q5.
The amount of power the controller is capable of
dissipating depends on many factors, including the V
CC
capacitor value, airflow conditions, proximity of the
controller to other heat generating components on the board,
and the layout of the metal traces on the board and their heat
spreading characteristics. To determine the thermal
characteristics of the controller in the application, the
evaluation board is placed in a controlled ambient
temperature and the V
HV
that results in temperature
shutdown is measured. R
q
JA
of the controller is given by
Eequation 22,
R
q
JA
+
T
SHDN
*
T
A
P
DSS
(eq. 22)
where T
A
is the ambient temperature of the system and
T
SHDN
is the junction temperature at which a thermal
shutdown (TSD) fault occurs. For the evaluation board, with
the HV pin tied directly to V
bulk
, a V
HV
of 257 V results in
a TSD event, and R
q
JA
is calculated as 82.5
°
C/W.
It is common to include a resistor, R
bulk
, in series between
the bulk voltage and the HV pin to spread the power
dissipation between the controller and R
bulk
. R
bulk
often
consists of at least two resistors in series for protection
against shorted component testing. The same power
dissipation limit is imposed on the controller as in the case
where no series resistor is used. Therefore, adding R
bulk
allows the maximum bulk voltage to increase by dissipating
the difference in the power while the startup circuit is
charging C
CC
. The increased bulk voltage is given by
Equation 23,
V
bulk
+
P
DSS
I
CC3
)
I
start
@
R
bulk
(eq. 23)
where P
DSS
is found by rearranging Equation 22 and using
the R
q
JA
measured above.
When adding the series resistors, it is recommended to
maintain a minimum V
HV
of 40 V to ensure there is enough
headroom to allow the startup circuit to supply I
start
to the
V
CC
pin. Therefore, at low line, the resistance between the
bulk voltage and the HV pin can not exceed that given by
Equation 24,
R
bulk
v
ǒ
V
bulk(min)
*
40 V
Ǔ
I
start(min)
(eq. 24)
where I
start(min)
is the specified minimum startup current
provided to the V
CC
pin. I
start(min)
= 5 mA and assuming
V
bulk(min)
= 90 V, the added series resistance should be no
more than 10 k
W
. For the evaluation board, R
bulk
is chosen
as 3.6 k
W
so that I
start
is 14.7 mA across the input voltage
range. For this evaluation board, with R
bulk
= 3.6 k
W
, I
start
= 14.7 mA and a maximum ambient temperature of 85
°
C,
the resulting maximum V
bulk
is 310 V, a 53 V increase in
comparison to the limit when connecting directly to the bulk
voltage.
The power dissipated by R
bulk
during the DSS cycle is
found using the rms current supplied through the startup
circuit during the DSS cycle, given by Equation 25,
P
Rbulk
+
R
bulk
@
ǒ
I
start(RMS)
Ǔ
2
(eq. 25)
Option 3 – Half
−
Wave Rectified Connection
To reduce the power dissipation of DSS mode at high
input voltage, the HV pin is connected to the half
−
wave
rectified node of the bridge rectifier in place of the bulk
voltage. Figure 6 illustrates this configuration.
Figure 6. V
CC
Connection with Full
−
time DSS Mode
Supplied By the Half
−
Rectified Sine Wave
Skip/
latch
FB
CS
DRV
GND
VCC
HV
NCP1219
D12
V
out
The average voltage applied to the HV pin is reduced
because, during half of the input voltage cycle, the HV
voltage is a function of the input sinusoid and the other half
of the cycle the input voltage is zero. The half
−
wave
rectified waveform is illustrated in Figure 7.
Figure 7. Half
−
Wave Rectified Waveform
V
peak
V
AVG, (half-wave)
time
Half-Wave
Rectified
Voltage
