KAC−12040
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23
8 Bank Pixel Order
The KAC−12040 always processes two rows at a time.
Even row decodes are sent to the bottom ADC and LVDS
output banks (0, 2, 4, 6). Odd rows are sent to the top ADC
and LVDS banks (1, 3, 5, 7). The ROI must be (and is
internally forced to) an even size and always starting on an
even row decode.
The rows are read out progressively left to right (small
column address to large). Eight pixels are sent out of the chip
at once, one pixel per LVDS bank per LVDS clock cycle.
Pixel Readout order:
1. Two rows are selected, the even row is sent to
the bottom ADC and the odd row to the top ADC.
2. Each ADC converts its row of pixel data at once
and stores the result in a line buffer.
3. At default settings there are 4 output LVDS banks
for each ADC.
4. Each LVDS Bank outputs one pixel per clock
cycle, so 4 pixels of each row are output each full
LVDS clock cycle, two rows in parallel for
8 pixels per clock cycle total.
5. The pixels are sent out from left to right
(low column number to high column number).
So the first 4 pixels are sent out on clock cycle 1,
and the next 4 pixels to the right are sent out on
clock cycle 2.
6. To conserve the number of wires per port,
the 10 bits per pixel are sent out DDR (Dual Data
Rate) over 5 ports. On the falling edge the upper
5 MSB bits are sent out, and on the rising edge the
lower 5 bits LSB are sent out. Completing one full
LVDS clock cycle and one set of eight pixels.
Figure 20. Pixel Readout Order Diagram
Bank 0
Bank 1
Row 2n +1
Row 2n
First CLK−DATA
Pulse
Second CLK−DATA
Pulse
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
Bank 2
Bank 4
Bank 6
Bank 3
Bank 5
Bank 7
Table 14. PIXEL READOUT ORDER TABLE
LVDS Bank
Row
Pixel Number
Bank 0
2n (Even)
0
4
8
12
16
Bank 2
2n (Even)
1
5
9
13
17
Bank 4
2n (Even)
2
6
10
14
18
Bank 6
2n (Even)
3
7
11
15
19
Bank 1
2n+1 (Odd)
0
4
8
12
16
Bank 3
2n+1 (Odd)
1
5
9
13
17
Bank 5
2n+1 (Odd)
2
6
10
14
18
Bank 7
2n+1 (Odd)
3
7
11
15
19
LVDS Clock Cycle
1
2
3
4
5
