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EZAIRO 7160 SL HYBRID

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Connection Diagram

The following connections should be observed when the Ezairo 7160 SL is used in typical hearing aid applications:

Figure 5. Connection Diagram, Bottom View

Ezairo 7160 SL

F10

E10

D10

C10

B10

A10

VSSRF2

VSSRF3

VSSRF4

VBAT

DGND

NRESET

DIO21

SCL

SDA

RCVRBAT

VSSRF1

VSSRF5

RFIO12

VDDO2

DIO9

DIO6

DIO20

RCVR1N

RCVR0N

HGND

JTCK

VDBL

DIO8

DIO5

DIO22

RCVR1P

RCVR0P

DIO29

VSSA

JTMS

RFNRESET

DIO4

DIO7

EXTCLK

DIO23

DIO24

XTAL32KN RESERVED RFGND2

AOUT

RFIO0

RFIO1

GND_MIC

VMIC

Audio In

AGND

XTAL32KP

VDCRF

RFGND1

RFIO2

VCCRF

RFIO3

Telecoil

Front Mic

Rear Mic

VREG

Receiver

Battery

Programming Strip

Volume/

Volume/Memory

−

Front Microphone

Rear Microphone

Telecoil

TP
TP

Direct Audio Input

Telecoil Reed Switch

ARD1

ARD0

Optional Receiver Detection Connections

Ezairo 7160 SL Pre Suite Connection Diagram

1.5pF

1.8nH

3nH

1.5pF

Antenna and matching circuit

XTAL32

(bottom view)

NOTE:

−

ON Semiconductor recommends to use the 9HT12

−

32.768KDZF

−

T SMD crystal from TXC corporation.

−

Harmonic filter on RF pin required to pass regulatory emission tests

−

For the purposes of BT

−

SIG certification, the following signals must be accessible or brought out to solderable test points: VBAT,

GND, and either RFIO2 & RFIO3 or DIO24 & DIO29. (Please see AND9838/D for more details)

Содержание EZAIRO 7160 SL

Страница 1: ...medical applications With its Arm Cortex M3 processor and LPDSP32 DSP core RSL10 supports Bluetooth low energy technology and 2 4 GHz proprietary protocols Development Tools Ezairo Preconfigured Suite Pre Suite The Ezairo Pre Suite provides a complete framework to easily develop Ezairo based hearing aids and fitting software Included in the Ezairo Pre Suite is a pre loaded firmware bundle configur...

Страница 2: ...efault clock calibration 12 80 MHz and 15 36 MHz to optimize the computing performance versus power consumption ratio The calibration entries for these 12 clock speeds are stored in the manufacturing area of the EEPROM Ultra high Fidelity 85 dB system dynamic range with up to 110 dB input signal dynamic range exceptionally low system noise and low group delay Ultra low Power Consumption 0 7 mA 10 ...

Страница 3: ...tery The system clock SYS_CLK was set to 5 12 MHz and an audio input sampling frequency of 16 kHz was used Parameters marked as screened are tested on each chip Table 2 ELECTRICAL SPECIFICATIONS Description Symbol Conditions Min Typ Max Units Screened OVERALL Supply Voltage VBAT Supply voltage measured at the VBAT pin 1 18 Note 3 4 1 25 2 0 V I O Supply Voltage Domain 2 VDDO2 1 05 3 3 V Current co...

Страница 4: ..._CTRL 0x7 15 mA Load regulation LOADREG VBAT 1 2 V 100 mA Iload 3 mA 4 10 mV mA Line regulation LINEREG VBAT 1 2 V Iload 100 mA 6 20 mV V VDDC Digital supply output volt age trimming range VDDC Control register configured typical values unloaded 0 72 Note 5 1 32 V n VDDC output level adjust ment VDDCSTEP 1 5 2 5 3 mV n Regulator PSRR VDDCPSRR 1 kHz VBAT 1 25 V 25 30 dB Load current ILOAD Delivered...

Страница 5: ...B 85 24 dB 82 27 dB 82 30 dB 80 33 dB 77 36 dB 74 Input peak THD N INTHD N Gain between 0 and 30 dB 10 dBFS signal 1 kHz 68 dB n Input peak THD N INTHD N Gain between 33 and 36 dB 10 dBFS signal 1 kHz 66 dB OUTPUT DRIVER Maximum peak current IDO High Power mode 25 mA Output impedance RDO Normal mode Iload 1 mA 4 5 5 5 W Output impedance RDO High Power mode 2 5 4 W Output dynamic range DODR Normal ...

Страница 6: ...emperature range of 0 to 50 C 1 5 1 5 Recommended working frequency SYS_CLK For recommended VDDC and VDDM 1 28 15 36 MHz Oscillator period jitter RMS at System clock 1 28 MHz before multiplication 400 ps PLL lock time For an input phase error 2 input reference clock of 128 kHz output clock of 2 56 MHz 10 ms n PLL tracking range 2 2 LOW DELAY PATH Group Delay Using the low delay path of the Filter ...

Страница 7: ...L10 ELECTRICAL SPECIFICATIONS Current consumption RX IVBAT Rx Mode ON Semiconductor proprietary audio streaming protocol at 7 kHz audio BW 37 ms delay 1 15 mA Standby Mode current Istb Digital blocks and memories are not clocked and are powered at a reduced voltage 30 mA Peak Current consumption at 1 Mbps IBATRFRX VDDRF 1 1 V 100 duty cycle 5 6 mA Rx Sensitivity 1 Mbps BLE 0 1 BER Single ended on ...

Страница 8: ... VSSRF RF analog ground A2 VSSRF RF analog ground A3 VSSRF RF analog ground A4 VBAT Power Supply A5 DGND Digital ground for the Ezairo 7100 A6 NRESET Reset pin for the Ezairo 7100 A7 DIO21 Digital Input Output 21 for the Ezairo 7100 A8 SCL Debug Port Clock for the Ezairo 7100 A9 SDA Debug Port Data for the Ezairo 7100 A10 RCVRBAT Output Stage Power Supply for the Ezairo 7100 B1 VSSRF RF analog gro...

Страница 9: ...TCLK EXT_CLK pin for the Ezairo 7100 D9 DIO23 Digital Input Output 23 for the Ezairo 7100 D10 DIO24 Digital Input Output 24 for the Ezairo 7100 E1 XTAL32KN Xtal input pin for 32 kHz xtal E2 RES RESERVED E3 RFGND RF Ground for RSL10 E4 AOUT Analog test pin E5 RFIO0 Digital Input Output 0 for the RSL10 E6 RFIO1 Digital Input Output 1 for the RSL10 E7 GND_MIC Input Transducer Ground for the Ezairo 71...

Страница 10: ...EZAIRO 7160 SL HYBRID www onsemi com 10 Figure 2 Ezairo 7160 SL Hybrid Schematics ...

Страница 11: ...EZAIRO 7160 SL HYBRID www onsemi com 11 Figure 3 Ezairo 7160 SL Hybrid Schematics Figure 4 Ezairo 7160 SL Keep out Area TOP LAYER KEEPOUT ...

Страница 12: ... RFGND2 AOUT RFIO0 RFIO1 GND_MIC VMIC Audio In AGND XTAL32KP VDCRF RFGND1 RFIO2 VCCRF RFIO3 Telecoil Front Mic Rear Mic VREG Receiver Battery Programming Strip Volume Memory Volume Memory TP TP Front Microphone Rear Microphone Telecoil TP TP TP TP TP Direct Audio Input Telecoil Reed Switch ARD1 ARD0 Optional Receiver Detection Connections Ezairo 7160 SL Pre Suite Connection Diagram w 47μF 1 5pF 1 ...

Страница 13: ...her information on the usage of the HEAR please refer to the HEAR Configurable Accelerator Reference Manual The HEAR is optimized for advanced hearing aid algorithms including but not limited to the following Dynamic range compression Directional processing Feedback cancellation Noise reduction To execute these and other algorithms efficiently the HEAR excels at the following Processing using a we...

Страница 14: ...are debugger for the Ezairo 7100 system that is always enabled regardless of the configuration of the general purpose I2C interface The debug port implements an Arm Cortex M3 processor debug port protocol command set that is tightly coupled with the Arm Cortex M3 processor and the memory components attached to this core The default address is 0x40 The Arm Cortex M3 processor of the RSL10 can be de...

Страница 15: ...ound in the manufacturing area of the EEPROM at address 0x00F1 to 0x00F2 2 bytes 16 bits Similar to the Ezairo 7100 information the hybrid ID can be retrieved using a programming interface Hybrid ID 0x03C0 0x13C0 for usage with special audio protocol Please contact your ON Semiconductor representative for more information Solder Information The Ezairo 7160 SL hybrid is constructed with RoHS compli...

Страница 16: ... streamer to the hearing aid using Ezairo 7160 SL While audio is streamed to the hearing aids the user is able to control the hearing device from a smartphone Company or Product Inquiries For more information about ON Semiconductor products or services visit our web site at http onsemi com Technical Contact Information dsp support onsemi com Datasheet Document Classification Advanced Information D...

Страница 17: ...l performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts ON Semiconductor does not convey any license under its patent rights nor the rights of others ON Semiconductor products are not designed intended or authorized for use as a critical component in life support systems or any FDA Class 3 medical ...

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