ON Semiconductor AR0331 Series, Общее описание устройства

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AR0331
www.onsemi.com
41
ELECTRICAL SPECIFICATIONS
Unless otherwise stated, the following specifications
apply under the following conditions:
•
V
DD
= 1.8 V – 0.10/+0.15; V
DD
_IO = V
DD
_PLL = V
AA
= V
AA
_PIX = 2.8 V
±
0.3 V;
•
V
DD
_SLVS = 0.4 V – 0.1/+0.2; T
A
= − 30 ° C to +85 ° C;
output load = 10 pF;
•
frequency = 74.25 MHz; HiSPi off.
Two-Wire Serial Register Interface
The electrical characteristics of the two-wire serial
register interface (S
CLK
, S
DATA
) are shown in Figure 44 and
Table 21.
Figure 44. Two-Wire Serial Bus Timing Parameters
S
Sr
t
SU;STO
t
SU;STA
t
HD;STA
t
HIGH
t
LOW
t
SU;DAT
t
HD;DAT
t
f
S
DATA
S
CLK
P
S
t
BUF
t
r
t
f
t
r
t
HD;STA
Note: Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register address are issued.
Table 21.
TWO − WIRE SERIAL BUS CHARACTERISTICS
(
f
EXTCLK = 27 MHz; V
DD
= 1.8 V; V
DD
_IO = 2.8 V; V
AA
= 2.8 V; V
AA
_PIX = 2.8 V; V
DD
_PLL = 2.8 V; V
DD
_DAC = 2.8 V; T
A
= 25
°
C)
Parameter Symbol
Standard Mode Fast Mode
Unit
Min Max Min Max
S
CLK
Clock Frequency
f
SCL 0 100 0 400 KHz
Hold Time (Repeated) START Condition
After this period, the first clock pulse is generated
t
HD;STA 4.0 − 0.6 − μ S
LOW Period of the SCLK Clock
t
LOW 4.7 − 1.3 − μ S
HIGH Period of the SCLK Clock
t
HIGH 4.0 − 0.6 − μ S
Set up Time for a Repeated START Condition
t
SU;STA 4.7 − 0.6 − μ S
Data Hold Time
t
HD;DAT 0
(Note 4)
3.45
(Note 5)
0
(Note 6)
0.9
(Note 5)
μ S
Data Set-up Time
t
SU;DAT 250 − 100
(Note 6)
− nS
Rise Time of Both S
DATA
and S
CLK
Signals
t
r − 1000 20 + 0.1Cb
(Note 7)
300 nS
Fall Time of Both S
DATA
and S
CLK
Signals
t
f − 300 20 + 0.1Cb
(Note 7)
300 nS
Set-up Time for STOP Condition
t
SU;STO 4.0 − 0.6 − μ S
Bus Free Time between a STOP and START
Condition
t
BUF 4.7 − 1.3 − μ S
Capacitive Load for Each bus Line Cb − 400 − 400 pF
Serial Interface Input pin Capacitance CIN_SI − 3.3 − 3.3 pF
S
DATA
Max Load Capacitance CLOAD_SD − 30 − 30 pF
S
DATA
Pull-up Resistor RSD 1.5 4.7 1.5 4.7 K Ω
1. This table is based on I
2
C standard (v2.1 January 2000). Philips Semiconductor.
2. Two-wire control is I
2
C-compatible.
3. All values referred to V
IHmin
= 0.9 V
DD
and V
ILmax
= 0.1 V
DD
levels. Sensor EXCLK = 27 MHz.
4. A device must internally provide a hold time of at least 300 ns for the S
DATA
signal to bridge the undefined region of the falling edge of S
CLK
.