
Maxiflex T2 CPU User Manual
22
-© Omniflex
UMM124XBR04.pdf
Example of Serial Port DIP switch setting
8
1 2 3 4 5 6 7
ON
[ White square indicates position of switch lever ]
Switches 1-5 = ID
This is set as a binary number with Switch 1 the least significant bit, and Switch
5 the Most significant bit.
In this example an address of 2 is selected.
Switch 6 reserved
.
(always leave switched off)
Switch 7 Default Conet/s (19200 baud) Protocol Select
.
Switch on to set Conet/s default mode of operation
In this example this switch is shown OFF.
Switch 8: Default Modbus ASCII (9600 baud) Protocol Selection
Switch 8 ON = Modbus ASCII slave at 9600 baud
(Data bits: 7;Parity: none; Stop bits: 1)
Switch 8 OFF = Internal protocol configuration
In this example, the Switch 8 is shown in the ON position to set the serial port to
its default configuration of MODBUS Slave Ascii at 9600.baud.
Set as shown, (switches 2 and 7 on) the serial port will operate as a Modbus ASCII
slave port at 9600 baud, and will respond to the slave address of 2.
Table 4.1: Serial Port default Address switch settings
4.5.1.3.
Modbus Data Register Mapping
A facility of the Modbus Protocol provides the ability to map the Modbus
Data types (such as coils and holding Registers) to specific areas of the
CPU’s DIT. See the DIT Layout (see section 5.1) and the dvx Template file
help for more details.
4.5.1.4.
Modbus Compressed DIT Addressing
An additional feature provided for the Modbus Protocol is “Compressed DIT
addressing”.
The standard layout of the Data Interchange Table provides 4000 registers
for each Module Slot on a Maxiflex base (see section 5.1).
Some Modbus Master devices are pre-programmed with a maximum
allowable range of 10,000 holding registers. This makes it impossible to
access the DIT registers in I/O slots from Slot 3 onwards (DIT addresses
12,000 upwards).
This feature allows the user to select a smaller number of registers for
access from Modbus in each slot, allowing the Modbus holding register
addressing to be compressed to fit into the 10,000 holding register limit
imposed.
The CPU slot must always be allocated 4000 registers, and so the I/O
module in Slot 1 must start at address 4000. If the start address for this
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