The attenuated CLOCK signal transitions occur b9V to +5V, so
the top comparator is biased at about +6V to detect it. This detected
signal, called CK (clock), is used to gate the shift register CD4015 U5
and the CD4021 parallel-to-serial converters U12-U27.
The attenuated DIGISTROBE signal is b9V and +2.5V, thus the
threshold for the next comparator is about +4V. The detected signal is
called DSTR (digital strobe) and it is used to reset the CD4015 shift
register and set the state of flip flop CD4013 U10 to the state of DIGITAL
multiplexer ON, ANALOG multiplexer OFF.
The attenuated ANASTROBE is sensed by the lower comparator, whose
threshold is set to about 1V. The resulting signal, ASTR (analog strobe)
is used to reset flip flop U10 to the ANALOG multiplexer ON, DIGITAL
multiplexer OFF mode, and reset the CD4024 analog address generator.
6.2.3 Digital Data Acquisition
When a DSTR is sensed, the flip-flop U10 turns on the CD4051 U8 and
resets the serial shift register U5. The first clock pulse (CK) causes the
shift register U5 to advance its D input (pin 15) to its first output, Q0 pin
13. This Q0 high state is inverted by one of the dates in CD4011 U6 and
latches all of the edge-triggered CD4021s connected to the LATCH UB
(latch upper bus) line when the gate transition from low to high occurs.
Since state Q1 on the CD4015 is still low, the LOEWR BUS BAR is in the
LOW state while the UPPER BUS BAR is in the HIGH state as a
consequence of the CD4049 inverter U7 which buffers the Q1 pin. Thus,
all keys that are not down,
i.e.
on the UPPER BUS BAR, will be latched
as a HIGH state on the LATCH UB CD4021s.
When the next clock pulse (CK) occurs, the CD4015 advances one more
state so that Q0 and Q1 are now both high. Thus, the UPPER BUS is
now LOW while the LOWER BUS is now high. When the next clock
comes along, CD4015 Q2 output goes high and on this transition, the
LATCH LB CD4021s are loaded with the state of the contacts, which if
they’re down,
i.e.
on the LOWER BUS BAR, will be latched as a HIGH
state on the LATCH LB CD4021s.
At this point, all of the UPPER BUS CD4021s have HIGH logic states at
the points where keys were not pressed, all of the LOWER BUS
CD4021s have HIGH logic states where all keys were fully pressed, and
those positions where neither slot is high correspond to keys in transition.
When the next clock comes along, the CD4015 advances a HIGH to the
Q3 output, which gates the CK line onto the CD4021 clock inputs. This
enables the CK line to shift out the data that was loaded during the first
