NXP Semiconductors T2080RDB-PC, Руководство пользователя, Страница: 7 / 47

Table 1-2. Acronyms and abbreviations (continued)
Usage Description
UART Universal Asynchronous Receiver/Transmitter
VCC Voltage for Circuit
VTT Voltage for Terminal
1.3 T2080 silicon features
The T2080 silicon features are as follows:
• Four e6500 cores, built on Power Architecture technology, sharing a 2 MB L2 cache
• 512 KB CoreNet Platform cache (CPC)
• Hierarchical interconnect fabric:
• CoreNet fabric supporting coherent and non-coherent transactions with
prioritization and bandwidth allocation amongst CoreNet endpoints
• Queue Manager (QMan) fabric supporting packet-level queue management and
quality of service scheduling
• One 32/64-bit DDR3 SDRAM memory controller:
• DDR3 and DDR3L with ECC and interleaving support
• Memory pre-fetch engine
• Data Path Acceleration Architecture (DPAA) incorporating acceleration for the
following functions:
• Packet parsing, classification, and distribution (Frame Manager 1.1)
• Queue management for scheduling, packet sequencing, and congestion
management (Queue Manager 1.1)
• Hardware buffer management for buffer allocation and de-allocation (Buffer
Manager 1.1)
• Cryptography Acceleration (SEC 5.2)
• RegEx Pattern Matching Acceleration (PME 2.1)
• Decompression/Compression Acceleration (DCE 1.0)
• DPAA chip-to-chip interconnect, using RapidIO Message Manager (RMan 1.0)
• 16 SerDes lanes at up to 10 GHz.
• Eight Ethernet interfaces, supporting combinations of:
• Up to four 10 Gbit/s Ethernet MACs
• Up to eight 1 Gbit/s Ethernet MACs
• Up to four 2.5 Gbit/s Ethernet MACs
• IEEE 1588 standard support.
• High-speed peripheral interfaces:
Chapter 1 Overview
QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 0, 04/2016
Freescale Semiconductor, Inc. 7