NXP Semiconductors T2080RDB-PC, Руководство пользователя, Страница: 37 / 47

Chapter 3
CPLD Specification
This section explains the CPLD registers.
3.1 CPLD Memory Map
memory map
Offset
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
0 Chip ID1 register (CHIPID1) 8 R 55h 3.1.1/37
1 Chip ID2 register (CHIPID2) 8 R AAh 3.1.2/38
2 Hardware version register (HWVER) 8 R See section 3.1.3/38
3 Software version register (SWVER) 8 R See section 3.1.4/39
10 Reset control register (RSTCON) 8 w1c See section 3.1.5/39
11 Flash control and status register (FLHCSR) 8 R/W See section 3.1.6/40
12 Thermal control and status register (THMCSR) 8 R/W See section 3.1.7/40
13 Panel LED control and status register (LEDCSR) 8 R/W See section 3.1.8/41
14 SFP+ control and status register (SFPCSR) 8 R/W See section 3.1.9/41
15 Miscellanies control and status register (MISCCSR) 8 R/W See section 3.1.10/42
16 Boot configuration override register (BOOTOR) 8 R/W See section 3.1.11/43
17 Boot configuration register 1 (BOOTCFG1) 8 R/W See section 3.1.12/43
18 Boot configuration register 2 (BOOTCFG2) 8 R/W See section 3.1.13/43
3.1.1 Chip ID1 register (CHIPID1 )
Address: 0h base + 0h offset = 0h
Bit 0 1 2 3 4 5 6 7
Read CHIPID1
Write
Reset
0 1 0 1 0 1 0 1
QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 0, 04/2016
Freescale Semiconductor, Inc. 37