NXP Semiconductors S32R27, Руководство по конструкции аппаратуры

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• Widen spacing between signal lines as much as routing restrictions will allow. Try not to bring traces closer than
three times the dielectric height.
• Design the transmission line so that the conductor is as close to the ground plane as possible. This technique will
couple the transmission line tightly to the ground plane and help decouple it from adjacent signals.
• Minimize parallel run lengths between single-ended signals. Route with short parallel sections and minimize long,
coupled sections between nets.
• For a single-ended trace, like clock transmission lines can be improved using the following guidelines:
• Keep clock traces as straight as possible. Use arc-shaped traces instead of right-angle bends.
• Do not use multiple signal layers for clock signals.
• Do not use via in clock transmission lines. Via can cause impedance change and reflection.
• Place a ground plane next to the outer layer to minimize noise. If you use an inner layer to route the clock trace,
sandwich the layer between reference planes.
• Terminate clock signals to minimize reflection.
• Use point-to-point clock traces as much as possible.
Appendix A Revision History
Table A-1 summarizes revisions to this document.
Table A-1. Revision History
Rev Date Description of Changes
0 03/2016 • Initial release.
1 04/2018 • In Introduction updated the text to include S32R37 products.
• In S32R family package options overview updated the text to include S32R37 package options.
Added Table 3 .
• In Power supply and sub sections:
• Added text to include S32R37 considerations for supply pins, decoupling and regulation
modes.
• Added further recommendations on supply ramping and combination in internal regulation
modes.
• Updated Figure 5 to show external monitor control of VREG_POR_B.
• Added clarification for C7 capacitance for external SMPS components.
• Changed reference from VDD_LV_DRFPLL to VDD_LV_LFASTPLL
• Added some further recommendations to power up sequence.
• In Connecting external clock sources updated the figures to include S32R37.
• In Recommended debug connectors and connector pin-out definitions added updates to show
S32R37 141BGA package limitations.
• Updated Table 14 to show S32R37 muxing.
• In RADAR analog front end and sub sections updated text to include include S32R37 devices and
in Table 20 added relaxation of SD_R requirement.
• In MIPI CSI2 interface added updates to show S32R37 considerations and package connections.
• Added Table 35 to show all variants pads for each recommendation.
S32R27/37 Hardware Design Guide, Rev. 1, 04/2018
NXP Semiconductors 49