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8.6 AFE pin configuration when not using on-board ADC's and

DAC

For an application which utilizes the MIPI-CSI2 interface to provide raw ADC data to the S32R274 device the unused pads
for the on board SD-ADC's and DAC, along with associated supplies must be configured as shown in

operation of the device. These connections also apply to the S32R372 257 MAPBGA package since this is pin compatible
and does not contain the on-board ADC's.

Table 20. AFE Pin Requirements when using off-chip ADC/DAC

Pin Number

Pin Name

Requirement

A1

SD_0_ADCN

Connect to SD_0_ADCP and leave floating (or N.C for S32R372)

A2

SD_1_ADCN

Connect to SD_1_ADCP and leave floating (or N.C for S32R372)

A3

SD_2_ADCN

Connect to SD_2_ADCP and leave floating (or N.C for S32R372)

A4

SD_3_ADCN

Connect to SD_3_ADCP and leave floating (or N.C for S32R372)

B1

SD_0_ADCP

Connect to SD_0_ADCN and leave floating (or N.C for S32R372)

B2

SD_1_ADCP

Connect to SD_1_ADCN and leave floating (or N.C for S32R372)

B3

SD_2_ADCP

Connect to SD_2_ADCN and leave floating (or N.C for S32R372)

B4

SD_3_ADCP

Connect to SD_3_ADCN and leave floating (or N.C for S32R372)

C1

SD_CM

1 μF Capacitor to Ground

C2

SD_R

Can be relaxed to 40k-47k Ohm +/- 10%

C5

DAC_C

Not used, leave floating

C7

DAC_AP

Not used, leave floating

C8

DAC_AN

Not used, leave floating

D4

AFE_FILTER

0.1 & 1 μF Capacitor to Ground

C3

VDD_LV_RADARREF

1uF Capacitor to Ground

D1

VDD_HV_RAW

3.3 V

D2

VSS_HV_RAW

Tied to Ground

D8

VDD_HV_DAC

3.3 V

D7

VSS_HV_DAC

Tied to Ground

E4

VDD_LV_SDADC

0.47 μF Capacitor to Ground

C4

VSS_LV_SDADC

Tied to Ground

D3

VDD_LV_RADARDIG

1 μF Capacitor to Ground

E3

VSS_LV_RADARDIG

Tied to Ground

F3

VDD_LV_OSC

0.1 & 1 μF Capacitor to Ground

F2

VSS_LV_OSC

Tied to Ground

E1

XOSC_XTAL

Differential clock supplied from external differential or -

F1

XOSC_EXTAL

Differential clock supplied from external differential source - or +

E2

VDD_LV_SDPLL

0.1 & 1 μF Capacitor to Ground

F4

VSS_LV_SDPLL

Tied to Ground

G3

VDD_LV_SDCLK

0.1 & 1 μF Capacitor to Ground

G4

VSS_LV_SDCLK

Tied to Ground

Table continues on the next page...

RADAR analog front end

S32R27/37 Hardware Design Guide, Rev. 1, 04/2018

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Содержание S32R27

Страница 1: ...onnections and supply decoupling pins It also discusses configuration options for clock reset ADC modules and the RADAR analog front end as well as recommended debug and peripheral communication connections including MIPI CSI2 and other major external hardware required for the device The S32R family requires multiple external power supplies to operate The main cores internal logic requires a 1 25 ...

Страница 2: ... sheet for complete package dimensions and ball placement Drawings are also available on nxp com search for the case outline number shown in Table 2 Table 2 Package sizes Device Package Physical Size Case Outline Number Pitch S32R274 257 MAPBGA 14 x 14 mm 98ASA00081D 0 8 mm S32R372 257 MAPBGA 14 x 14 mm 98ASA00081D 0 8 mm S32R372 141 MAPBGA 10 x 10 mm 84ASA00768D 0 65 mm The table below shows the ...

Страница 3: ...d internal voltages are within the required operating ranges before the microcontroller can exit the reset state and enter operation The microcontroller offers a DC DC voltage regulator function as part of the power management controller PMC module 1 This regulator can be used to supply the digital low voltage required for the internal logic and other low voltage supplies The device can be configu...

Страница 4: ...mum SAR ADC performance it is recommended to have a ground plane below the VDD_HV_ADCREF0 2 traces 3 Internal regulation mode When using external regulation mode this domain can be tied to VDD_HV_PMU 4 The naming convention VDD_LV_LFASTPLL is equal to VDD_LV_DRFPLL Not present on S32R372 141MAPBGA Package 5 VDD_LV_IO_AURORA must be connected to the same voltage supply as VDD_LV_CORE The supplies m...

Страница 5: ...is configured in external regulation mode and supply is connected to VDD_HV_PMU For internal regulation mode see SMPS external component configuration The device has several pins for the connection to external decoupling capacitors for the analog front end Details of these can be found in RADAR analog front end 3 2 Decoupling capacitors layout priority When trade offs must be made in the schematic...

Страница 6: ...he PLL for the LFAST SIPI communication interface 4 VDD_HV_IO VDD_HV_PWM and VDD_LV_IO drive GPIO and other external communication interfaces Although it is still important that these supplies have a clean power signal the hardware they power is less affected by noise and they are considered of lower priority When completing the layout of decoupling capacitors care should be taken to reduce the vo...

Страница 7: ...e further information on this feature can be found in the PMC chapter in the device reference manual VREG_SEL is part of a collection of I O signals that relate to the VREG operation mode The other pins are mentioned in the table below Table 7 PMC Voltage regulator signals Signal Name Direction VREG Enabled Internal Mode VREG Disabled External Mode VREG_POR_B Input External power on reset If not u...

Страница 8: ...ltage detect LVD HVD circuits are enabled by default The internal POR will keep the device in reset until all the monitored supplies have reached their minimum operation threshold The internal POR function means that the external POR pin VREG_POR_B is not needed As such it is internally pulled up to the PMC supply voltage It can be left floating or alternatively connected to 3 3 V VREG_POR_B remai...

Страница 9: ... introduce noise into high fidelity analog components The external component layout is shown in Figure 3 Figure 3 SMPS external components layout Table 8 provides recommended values for the external components Table 8 External component values Component Label Recommended Value M1 SI3443 2SQ2315 L1 2 2 μH 3A 100 mΩ series resistance E g Bourns SRU8043 2R2Y D1 SS8P3L 8A Schottcky diode R1 24 kΩ C1 1...

Страница 10: ...osely as possible to the VDD VSS pins of the MCU as they guarantee the low impedance of the core MCU supply and also help to reduce the high frequency content of the Iload path The gate driver circuitry also forms important current loops that must be minimized not shown in Figure 3 For that purpose C8 C9 must be placed as close as possible to the gate driver supply pins The ground connections for ...

Страница 11: ... Board supply 5V 12V SAR ADC 3 3V low noise POR Lin VReg 3 3V low noise Lin VReg Lin VReg POR_B DC DC VReg AFE Internal Lin VRegs 3 3V low noise HV_PMU 3 3V HV_REG_3V8 HV_ADCRE F0 2 HV_ADC 1 25V HV_DAC HV_RAW DC DC VReg HV_FLA HV_IOx LV_CORE 1 25V 1 8A HV_IO_PWM External Monitor Figure 5 Supply connections This mode of operation can be selected by driving the VREG_SEL pin low 8 This disables the i...

Страница 12: ...ing the device data sheet as reference From this point it is assumed that internal regulation mode is being used unless where explicitly stated In external regulation mode the internal POR and LVD HVD are disabled by default but can be enabled by software after power up The function of the POR and LVD circuits is to hold the device in reset as long as the supply voltages to the LVD circuits are be...

Страница 13: ...is the combination of all internal POR signals from the analog PMC block When the critical power supplies are below minimum levels internal regulation mode or the VREG_POR_B pin is driven low the MCU is held in the POWERUP phase of the reset state machine POR asserted until the power supplies have reached specified levels When the required voltage levels are reached POR is deasserted and is input ...

Страница 14: ...g the power ramp They can be connected to the same voltage supply If VDD_HV_DAC and VDD_HV_RAW are supplied by 2 separate regulators the following must be met For RAW or DAC ramp rates less than 1ms VDD_HV_DAC comes on no earlier than 500 us before VDD_HV_RAW for RAW or DAC ramp rates greater than 1ms VDD_HV_DAC is below 2 0V at the time VDD_HV_RAW reaches 1 0 V Alternatively VDD_HV_DAC and VDD_HV...

Страница 15: ... OSC 40MHz XOSC_CLK SDPLL_CLK AFE XTAL EXTAL Figure 6 S32R family clock sources During power up the IRCOSC is the default clock for the system In normal operation software can then configure each of the system components to use one of the clock domains as the clock source The dual PLL must be enabled by software and can provide separate system and peripheral clocks PLL0 is the primary PLL driven b...

Страница 16: ...ely no high current or high speed signals should be run near any of the crystal components Other than the connections shown in the above schematics no other connections should be made to the crystal or EXTAL and XTAL device pins Do not use XTAL to drive any other circuitry than shown If an external single clock source is being used as clock reference to the MCU then the XTAL pin should be left flo...

Страница 17: ...d but an external pull up resistor to VDD_HV_IO should also be used A falling edge on this pin will trigger a functional reset to the Reset Generation Module RGM Forcing this pin low will keep the device in the last phase of the reset sequence Phase3 Functional In external voltage regulation mode VREG_POR_B allows external supply circuits to signal to the MCU when power is available so the power u...

Страница 18: ...terface support is required NOTE Whichever connector is chosen keep out areas may be required by some tools Consult the preferred tool vendor to determine any area that must remain clear around the debug connector Some tool vendors may include an extension cable to minimize keep out areas but use of an extension will degrade the signal In many cases this degradation will be insignificant but it de...

Страница 19: ...ries of connectors is intended for high speed applications requiring a minimum footprint size with a reliable latching connection The recommended connector has two rows of seventeen contacts each with a spacing of 0 8 mm The connector provides isolation between the high speed trace signals and the low speed JTAG and control signals It also provides ample ground connections to ensure signal integri...

Страница 20: ...taP TX1 7 8 TDI TxDataN TX1 9 10 TDO RxDataP VSS 11 12 JCOMP RxDataN TX2 13 14 EVTI1 TX2 15 16 EVTI0 VSS 17 18 EVTO0 TX3 19 20 VREG_POR_B TX3 21 22 RESET_B VSS 23 24 VSS TX4 1 25 26 CLK TX4 1 27 28 CLK VSS 29 30 VSS TX5 1 31 32 EVTO1 RDY TX5 1 33 34 N C VSS GND GND VSS 1 Reserved for TXn signals not currently used Recommended debug connectors and connector pin out definitions S32R27 37 Hardware De...

Страница 21: ...is additional circuitry connected to the Nexus JTAG pins or long traces that could be affected by other signals due to crosstalk from high current or high speed signals a minimum number of external pull resistors can be added to ensure proper operation under all conditions Table 13 Optional external pullups downs Nexus JTAG signal Resistor capacitor direction and value Description JCOMP 4 7 kΩ pul...

Страница 22: ... ADCs with a configurable number of channels up to 16 each but does not have any SDADC instances The SDADC where applicable is part of the RADAR analog front end and is detailed in Sigma Delta ADC This chapter will focus on the SAR ADCs The SAR ADCs receive input from 16 multiplexed pins Please refer to the Power supply section for information on how to connect the ADC power and reference pins Eac...

Страница 23: ... 10 Bandgap Reference PMC Bandgap Reference PMC Internal Channel 11 PB 9 GPIO_25 T3 PB 9 GPIO_25 T3 External Channel 12 PB 10 GPIO_26 R3 PB 10 GPIO_26 R3 External Channel 13 PB 11 GPIO_27 T2 PB 11 GPIO_27 T2 External Channel 14 PB 12 GPIO_28 U2 PB 12 GPIO_28 U2 External Channel 15 TSENS0 TSENS1 Internal 8 RADAR analog front end The S32R microcontroller family integrates a number of high performanc...

Страница 24: ...nd external circuitry is required to preserve signal integrity Filtered Output Bus Interface Decimation Filters x4 Modulator Output x4 14 bits x4 Conversion Complete x4 Control Registers Interrupts A D Input Pairs x4 Crystal Interface DAC Output Pair Powers Grounds Tank Capacitors Filter Enables DAC Data Clock Generation AFE Analog Block SDPLL Output 320 MHz 160 MHz 80 MHz clocks IPS Figure 14 AFE...

Страница 25: ... to VSS_LV_SDCLK VDD_LV_OSC External bypass capacitor for XOSC analog 1 4 V VREG 1 0 μF 0 1 μF grounded to VSS_LV_OSC VDD_LV_SDPLL External bypass capacitor for SD PLL analog 1 4 V VREG 1 0 μF 0 1 μF grounded to VSS_LV_SDPLL VDD_LV_RADARREF External bypass capacitor for 1 2 V from the VREF 1 0 μF grounded to VSS_LV_SDADC DAC_C DAC connection to external cap for noise filtering 10 μF connected to V...

Страница 26: ... to remove any DC bias present and allow the AC signal to pass through This ensures that the ADC s operate within their input range The recommended value for these capacitors is 0 22μF as shown in Figure 15 Figure 15 SD ADC AC coupling capacitors 8 3 Digital to Analog Converter The DAC is used to produce analog ramp signals for generation of RADAR waveforms Table 18 DAC signal description Name Pin...

Страница 27: ... Sigma Delta PLL There are no external connections required for the Sigma Delta PLL Information on configuration can be found in the Analog Front End chapter in the device reference manual 8 5 XOSC Instructions on how to connect an external source to drive the XOSC clock can be found in Connecting external clock sources Table 19 XOSC external connections Name Pin 257MBGA Pin 141BGA Direction Funct...

Страница 28: ...or S32R372 B3 SD_2_ADCP Connect to SD_2_ADCN and leave floating or N C for S32R372 B4 SD_3_ADCP Connect to SD_3_ADCN and leave floating or N C for S32R372 C1 SD_CM 1 μF Capacitor to Ground C2 SD_R Can be relaxed to 40k 47k Ohm 10 C5 DAC_C Not used leave floating C7 DAC_AP Not used leave floating C8 DAC_AN Not used leave floating D4 AFE_FILTER 0 1 1 μF Capacitor to Ground C3 VDD_LV_RADARREF 1uF Cap...

Страница 29: ...tended to be a very low cost and low performance interface This interface was originally specified with signal voltages of 12 V and 12 V typically However this has been lowered to a typical minimum voltage of 5 V and 5 V in recent years Figure 17 and Table 21 show the typical connections between the serial port of an MCU and the MAX3232 EP RS 232D transceiver from Texas Instruments http www ti com...

Страница 30: ... with an operating temperature range of 55 to 125 C Table 21 Typical RS 232D connector definition Pin number Description 1 Connect to pin 4 and 6 2 RS 232 TX Transmit 3 RS 232 RX Receive 4 Connect to pin 1 and 6 5 GND 6 Connect to pin 1 and 4 7 N C 8 N C 9 N C NOTE N C pins are not connected The shell of the connector should be connected through a ferrite bead to ground 9 2 Example LIN interface L...

Страница 31: ...LIN RXD LIN Receive Data Output to the MCU 2 EN Input Enable Control MCU GPIO Enables operation of the device 3 Wake Input Wake Input LIN Bus Wake1 Wake enables the devices out of sleep mode 4 TXD Input Transmit Data Input MCU LIN TXD LIN Transmit Data Input from the MCU 5 GND Input Ground System Ground Reference Device ground reference 6 LIN Input Output LIN Bus LIN bus Bidirectional pin that rep...

Страница 32: ...ent is available for the total number of LIN slaves that are powered through this connection In some systems this may come from the master LIN node Wake The Wake signal is typically used for each individual slave node to enable the LIN physical interface of that node and to consequently enable the power supply using the INH output to power up the MCU to perform some action For example when the han...

Страница 33: ...http www nxp com TJA1080A device is typically used as the FlexRay transceiver although others are also available One transceiver is required for each FlexRay channel Figure 19 and Table 25 below shows the typical connections using the TJA1080A MCU FR_x_TX MCU FR_x_TXEN MCU FR_x_RX MCU GPIO MCU_GPIO BP BM Vbatt 5V 3 3V 3 3V 10 μF 10K 47R 47nF 4700 pF 10K C21 33pF C21 33pF 10 μF 4700pF 47R 10 μF 47p...

Страница 34: ...t allows reception listen only mode 4 VIO Input power IO Power Supply 3 3 Volts Power supply input for the MCU I O signals 5 TXD Input Transmit Data MCU FR_x_TX1 Transmit data from the MCU for transmitting on the FlexRay bus Internal pullup 6 TXEN Input Transmit Enable MCU FR_x_TXEN1 Transmit enable A high level disables the transmitter Internal pullup 7 RXD Output Receive Data MCU FR_x_RX1 Receiv...

Страница 35: ... minus signal 18 BP Input Output Bus Line Plus To FlexRay Connector FlexRay bus plus signal 19 VCC Input power Supply Voltage 5 Volts Supply voltage for internal logic 20 VBUF Input power Buffer Supply Voltage 5 Volts Supply voltage for the FlexRay bus minus plus signals 1 x can be channel A or channel B To support the requirements of worldwide OEMs two connector types for FlexRay are used on eval...

Страница 36: ...5 SHIELD OPTIONAL Optional Shield if required 6 N C No connection 7 BP_A Bus Plus Channel A 8 BP_P Bus Plus Channel B 9 N C No connection NOTE A male type connector is used on the evaluation board and a female type cable connects with this The metal shell of the connector should be connected through a ferrite bead to GND Example communication peripheral connections S32R27 37 Hardware Design Guide ...

Страница 37: ...ight angle connector with flange for target system tin contacts latch 39 29 1028 Mating connector with latch for cable assemblies 39 01 2020 Female terminal for mating cable assembly 39 00 0077 9 4 CAN interface circuitry Controller Area Network CAN is commonly used in almost all automotive applications to allow communication between various microchips in the car A separate CAN transceiver is requ...

Страница 38: ...wn in the following table An example TJA1057 FD circuit is shown in this application note Table 29 NXP CAN transceiver comparison UJA1161 TJA1145 TJA1057 Frame data rate Kbit s 2000 2000 5000 Modes of operation Normal Standby Normal Listen only Standby Sleep Normal Listen only 9 4 1 CAN with flexible data rate TJA1057 interface The figure below shows the typical connections for the physical interf...

Страница 39: ...w CAN Bus Connector CAN bus low pin 7 CANH Input Output CAN Bus High CAN Bus Connector CAN bus high pin 8 S Input Silent Mode Grounded or MCU GPIO Silent mode control input A high level on this pin selects Silent mode This mode disables the transmitter but keeps the rest of the device active This may be used in case of an error condition 9 4 2 Recommended CAN connector Generally DB 9 connectors ar...

Страница 40: ...rential interface with one 2 wire clock Lane and one or more 2 wire data Lanes The MIPI CSI2 D PHY Rx receive only physical layer implemented on the S32R family is used not for image sensor data but to receive raw RADAR ADC data from an external RADAR front end with a compatible CSI2 D PHY interface The control interface for the physical layer is compatible with the SPI or the I2C standard dependi...

Страница 41: ...rection Description VDD_LV_D PHY D9 D9 B6 Power Input 1 2 V Supply for MIPI CSI2 D PHY VSS_LV_D PHY A10 A10 D8 Ground Ground for MIPI CSI2 D PHY VSS_LV_D PHY B10 B10 N A Ground Ground for MIPI CSI2 D PHY VSS_LV_D PHY C10 C10 N A Ground Ground for MIPI CSI2 D PHY VSS_LV_D PHY D10 D10 N A Ground Ground for MIPI CSI2 D PHY REXT C9 C9 B5 Input D PHY External resistor connection 15 kΩ 1 or lower CSI2_C...

Страница 42: ...ld be left floating and should not be tied to GND or power rails since this could cause damage to the part Due to the high speed nature of the interface care should be taken with the layout of the MIPI CSI2 signal traces Please see High speed layout considerations for more details No termination is required on the S32R MIPI CSI2 signal side 9 5 1 MIPI CSI2 recommended connector There is no standar...

Страница 43: ...thernet IEEE 802 3 networks It includes functionality to accelerate the processing of various common network layer protocols such as IP TCP and UDP An external transceiver interface and transceiver function are required to complete the interface to the media ENET is not supported on the S32R37X device 9 6 1 Ethernet MII RMII interface examples The figure below shows a typical set up of the complet...

Страница 44: ...l Name Description Direction MII RMII 7 Wire Port Options ENET_MDIO Management Data Input Output I O REQ N A N A PG 8 ENET_MDC Management Data Clock O REQ N A N A PG 9 ENET_RMII_CLK RMII Reference Clock Input Output I O N A REQ N A PG 11 ENET_TX_EN Transmit Enable O REQ REQ REQ PC 15 ENET_TXD0 Transmit Data 0 O REQ REQ REQ PD 0 ENET_TXD1 Transmit Data 1 O REQ REQ N A PD 3 ENET_TXD2 Transmit Data 2...

Страница 45: ...22 4 5 249 0 1UF 2 2K 0 1UF 22 3 6 22 2 7 49 9 1 8 2 2K 22 4 5 22 1 8 22 3 6 J61 HDR_1X3 1 2 3 0 1UF 22 1 8 0 1UF 2 2K 2 2K 49 9 2 7 R75 22 2 2K dp83848 U6 10 100 single phy RXCLK 38 RSVDPU2 21 RSVDPU1 20 RSVD5 12 RSVD4 11 RSVD3 10 RSVD2 9 RSVD1 8 RDN 13 RDP 14 LEDACTCOL_ANEN 28 IOVDD33_2 48 IOVDD33_1 32 IOGND_2 47 IOGND_1 35 DGND 36 AVDD33 22 AGND_2 15 AGND_1 19 TXD2 5 TXCLK 1 LEDLINK_AN0 26 RXER...

Страница 46: ... 3 ENET_TXD2 Transmit Data 2 O REQ PD 4 ENET_TXD3 Transmit Data 3 O REQ PG 10 ENET_TXCLK Transmit Clock I REQ PG 11 ENET_RXDV Receive Data Valid I REQ PD 2 PI 2 ENET_RXD0 Receive Data 0 I REQ PD 5 ENET_RXD1 Receive Data 1 I REQ PD 6 ENET_RXD2 Receive Data 2 I REQ PH 4 ENET_RXD3 Receive Data 3 I REQ PH 5 ENET_RXCLK Receive Clock I REQ PD 1 PH 13 Figure 29 shows an example circuit for interfacing th...

Страница 47: ...These pins must be must be left floating as connecting to power or ground can cause damage to the device Alternative Boot FAB D15 D15 C11 Input pin for selecting alternative boot modes Please see the Boot Assist Module BAM and System Status and Configuration Module SSCM chapters in the device reference manual for more information Alternative Boot ABS 0 L16 L16 H12 Input pin for selecting alternati...

Страница 48: ...ategy J1 J2 K1 K2 H1 H2 G1 G2 J1 J2 K1 K2 H1 H2 G1 G2 A1 A2 A3 A4 A5 A9 B1 B2 B3 B4 B5 B9 C1 C2 C5 C6 C7 C8 D3 D4 D5 D7 E3 E4 T8 T9 U8 U9 E1 E2 F2 F3 G2 G3 G1 H1 There are a number of non functional pins that must be dealt with appropriately 10 High speed layout considerations Due to the high speed nature of many of the interfaces on the S32R274 device attention has to be paid to the PCB layout to...

Страница 49: ...evisions to this document Table A 1 Revision History Rev Date Description of Changes 0 03 2016 Initial release 1 04 2018 In Introduction updated the text to include S32R37 products In S32R family package options overview updated the text to include S32R37 package options Added Table 3 In Power supply and sub sections Added text to include S32R37 considerations for supply pins decoupling and regula...

Страница 50: ...XP the NXP logo NXP SECURE CONNECTIONS FOR A SMARTER WORLD COOLFLUX EMBRACE GREENCHIP HITAG I2C BUS ICODE JCOP LIFE VIBES MIFARE MIFARE CLASSIC MIFARE DESFire MIFARE PLUS MIFARE FLEX MANTIS MIFARE ULTRALIGHT MIFARE4MOBILE MIGLO NTAG ROADLINK SMARTLX SMARTMX STARPLUG TOPFET TRENCHMOS UCODE Freescale the Freescale logo AltiVec C 5 CodeTest CodeWarrior ColdFire ColdFire C Ware the Energy Efficient So...

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