NXP Semiconductors S32R27, Руководство по конструкции аппаратуры

Страница: 15 / 50

4 Clock configuration
The S32R family system reference clock can be sourced in three ways: using the internal RC oscillator (IRCOSC),
connecting an external crystal or connecting an external oscillator (XOSC). To use XOSC, an external 40 MHz crystal or
oscillator must be connected through the XTAL and EXTAL pins. XTAL and EXTAL pins also support differential LVDS
clock inputs. Information on how to do this can be found in
Connecting external clock sources . IRCOSC or XOSC is used as
the clock source for the internal phase-locked loops (PLL) to generate the high frequency clocks for the cores and
peripherals.
This structure provides five different clock domains that are available as the source for system and peripheral clocks:
• IRCOSC - 16 MHz internal reliable RC oscillator
• XOSC - 40 MHz oscillator (using external crystal (XTAL) or external oscillator in bypass (EXTAL))
• PLL0 - up to 240 MHz PLL
• PLL1 - up to 240 MHz frequency-modulated (FM) PLL
• SDPLL- 320 MHz
11
PLL for the Sigma-Delta ADC
XOSC
40MHz
1-2ps Jitter
Bypass:
40MHz
FMPLL_1
VCO:600-
1250MHz
IRCOSC
16MHz
Cryst
40MHz
SDPLL
320MHz
IRC_CLK
PLL_CLK0
PLL_CLK1
PLL_0
VCO: 600-
1250MHz
OSC
40MHz
XOSC_CLK
SDPLL_CLK
AFE
XTAL
EXTAL
Figure 6. S32R family clock sources
During power up, the IRCOSC is the default clock for the system. In normal operation, software can then configure each of
the system components to use one of the clock domains as the clock source. The dual PLL must be enabled by software and
can provide separate system and peripheral clocks. PLL0 is the primary PLL driven by the reference clock and used to
provide a clock to the device modules. PLL1 is a frequency-modulated PLL (FMPLL) driven by PLL0 and is used to provide
the system clock. Alternatively, XOSC can be used to drive PLL1.
The most important aspects of an accurate clock source require that some care be taken in the layout and design of the
circuitry around the crystal and PLL power supplies. Any noise in these circuits can affect the accuracy of the clock source to
the PLL. The power supply for the PLL is taken from VDD_LV_PLL0. Noise on this supply can affect the accuracy and
jitter performance of the PLLs. In order to minimize any potential noise, it is recommended that the additional capacitors
recommended in
Table 5 are fitted to the VDD_LV_PLL0 supply.
11. Divided by 2 (160 MHz), and 4 (80 MHz) if used for system and peripheral clocks
Clock configuration
S32R27/37 Hardware Design Guide, Rev. 1, 04/2018
NXP Semiconductors 15