Table 7. Sample revision history (continued)
Revision number
Date
Substantive changes
1
06/2017
1. In
Table 1. Power domains and decoupling
capacitors
on page 2 Footnote is added in the table
2. In
Clock circuitry
on page 3 the value of Fast
internal reference clock is changed to 48MHz from
48-60MHz and value of External square wave input
clock changed to 50 MHz from 60 MHz
3. In
#unique_8/
unique_8_Connect_42_TABLE_WGL_5ZD_CZ
deleted the line (if not .........by MCU)
4.
External pin RESET
on page 11 changed from
When the RESET................. drain output to The
RESET pin....................output stage
5. In
Power supplies
on page 2
Figure 1.
on page 2
updated.
6. In
Clock circuitry
on page 3 When using the
external oscillator....the frequency range of the
external oscillator should be 4–40 MHz changed to
8–40 MHz
7. New chapter
Analog comparator interface
on page
11 added
2
02/2018
1. Updated the table
Table 1. Power domains and
decoupling capacitors
on page 2.
2. Added the following sections
Quad Serial
Peripheral Interface
on page 23,
Injection current
on page 31,
PCB layer stacking
on page 30,
Ethernet MAC Interface
on page 22
3
12/2018
1. Updated
Figure 1.
on page 2
2. In
Debug and programing interface
on page 5
removed the text "
Usually, MCUs do not include pull-up or pull-down
resistors on JTAG/SWD pins".
3. In
External pin RESET
on page 11 removed the
paragraph "In prototype designs.......330 pF are
recommended" and added "The reset line has
an ......pull-up resistor value" and "Despite a
capacitor in.....detected for the MCU".
4. Removed the column "Required pull-up / pulldown"
from
Table 3. JTAG signal description
on page 6.
5. In
External pin RESET
on page 11 removed the
figure "RESET circuit".
6. Updated
Unused pins
on page 26 and added a
note.
NXP Semiconductors
Revision history
Hardware Design Guidelines for S32K1xx Microcontrollers , Rev. 3, December 2018
Application Note
32 / 33
