signal integrity, avoid using multiple signal layers for data signal routing. All signal traces should have a continuous and solid
reference plane, either GND or VDD.
Clock Signal Routing: In high speed synchronous data transfer, good signal integrity in a PCB design is of critical importance,
especially for the clock signals, SCLK and DQS. When routing the clock signal, special cares should be taken. The following
practices are recommended.
• Run the clock signal at least -w3w of the trace width away from all other signal traces. This helps keep the clock signal clean
from crosstalk noise.
• Use as few via(s) as possible for the whole clock signal path. Vias cause impedance change and signal reflection.
• All signal traces should go with a solid reference plane, either GND or VCC.
• Run the clock trace as straight as possible and avoid using serpentine routing.
• Keep a continuous ground in the next layer as reference plane.
• Route the clock trace with controlled impedance.
• Keep the clock signal from disturbance or crosstalk by separating it from other signals by using wider spacing. Data bus
should be routed with matching length to the reference of the clock. The matching length is recommended to be within ± 50
mils.
Figure 26. Recommended clock signal routing
9 Unused pins
The unused digital and analog pins must be left floating. In software, the application should ensure that the ports function of the
MCU is 'DISABLED'. The DISABLED function is default state for all pins not initialized.
NXP Semiconductors
Unused pins
Hardware Design Guidelines for S32K1xx Microcontrollers , Rev. 3, December 2018
Application Note
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