Figure 24. External memory option - Single Quad Flash on the B-side
Data and Clock Signal Termination: Clock generation and distribution becomes more difficult as the speed and performance
of microprocessors increase to higher limits. Controlled and precise clocking distribution techniques are needed to maintain a
synchronous system. Clock signal quality and skew are the two major problems with distributing clock signals. With higher
frequencies, and the associated fast edge rates, long traces behave like transmission lines. Ring back, overshoot, and undershoot
occur as a result of poor termination of transmission lines. They contribute to bad signal quality, false switching, and they can
cause damage in extreme cases.
Given the effective output driver strength of 25-33 Ohms and the transmission line characteristic impedance of 50 Ohms, one
should add the termination resistor close to the output driver, to minimize the reflection as shown below.
Figure 25. Point-To-Point transmission line
Data Signal Routing: In order to keep the correct timing for the data transfer from the Microcontroller to the IC Memory, the PCB
data traces should be the same length and time delay as the clock trace from Microcontroller to the IC Memory. Data signals
should be routed with controlled impedance traces to reduce signal reflections. Avoid routing traces with 90 ° angle corners. The
recommendation is to cut the corner and smooth the trace when a trace route needs to change direction. To further improve the
NXP Semiconductors
Quad Serial Peripheral Interface
Hardware Design Guidelines for S32K1xx Microcontrollers , Rev. 3, December 2018
Application Note
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