Errata for Revision 1.1
MCF5235 Reference Manual Errata, Rev. 2.2
Freescale Semiconductor
5
2
Errata for Revision 1.1
Table 2. MCF5235RM Rev 1.1 Errata
Location
Description
Throughout
Remove overbar from DACKn signals, as they are not asserted low.
Table 2-1/Page 2-6
ERXER direction should be input, ETXEN direction should be output.
Table 2-1/Page 2-8
For 196BGA package, change pin F10 from OVDD to VSS.
Table 2-5/Page 2-10
Byte Strobes function column should say: “BS0 controls access to the least significant byte
lane of data, and BS3 controls access to the most significant byte lane of data.” and also
“Note that most SDRAMs associate DQM3 with the MSB, in which case BS3 should be
connected to the SDRAM's DQM3 input.”
Table 2-9/Page 2-12
ERXER direction should be input.
Table 2-14/Page 2-16
Add entry in table for PSTCLK output signal. “PSTCLK indicates when the development
system should sample PST and DDATA values.”
Figure 3-6/Page 3-17
Table 3-10/Page 3-18
The reset value of D0[DEBUG] is 0x0. The debug revision of the MCF5235 is Rev. A. Table
3-10 is incorrect as well.
Figure 3-7/Page 3-18
The reset value of D1[DCSIZ] is 0x0 and the reset value of D1[RAM1SIZ] is 0x8. Table 3-11
is correct
Section 7.1.3.5/Page 7-6
The PLL cannot be stopped when the device enters stop mode. Remove paragraphs 3-6
and add in their place “During stop mode, the PLL continues to run. The external
CLKOUT signal may be enabled or disabled when the device enters stop mode,
depending on the LPCR[STPMD] bit settings. The external CLKOUT output pin may be
disabled to lower power consumption via the SYNCR[DISCLK] bit. The external
CLKOUT pin function is enabled by default at reset.”
Table 7-3/Page 7-7
Footnote should read: “
In 1:1 mode for the MCF5235, f
sys
= 2
×
f
ref_1:1
”
Table 7-5/Page 7-9
The first equation in footnote #1 in the MFD bit description field is incorrect. It should be:
“f
sys
= f
ref
×
2(MFD + 2)/2
RFD
” instead of f
sys/2
.
Table 7-5/Page 7-9
The second equation in footnote #1 in the MFD bit description field is incorrect. It should be:
“f
ref
×
2(MFD + 2)
≤
150MHz” instead 75MHz
Section 7.4.3/Page 7-15
First paragraph, the default core frequency is one and a half times the reference frequency
after reset instead of two times the reference frequency. An MFD = 0b001 is 6x not 2x.
Table 7-11/Page 7-30
Delete 4th and 5th rows on this page, as the PLL cannot be disabled in stop mode.
Table 8-4/Page 8-4
The description of bits 2-0 is missing from the LPCR Field Description table. These should
be included with the following description: “Reserved, should be cleared.”
Section 8.3.2.3/Page 8-6
Corrected second paragraph since the core watchdog cannot reset the device. Second
paragraph should read “When enabled, the core watchdog can bring the device out of
low-power mode via a core watchdog interrupt. This system setup must meet the
conditions specified in Section 8.3.1, “Low-Power Modes” for the core watchdog interrupt
to bring the part out of low-power mode.”
Section 8.3.2.16/Page 8-10 The PLL cannot be stopped when the device enters stop mode. Remove paragraphs 2-5
and add in their place “During stop mode, the PLL continues to run. The external
CLKOUT signal may be enabled or disabled when the device enters stop mode,
depending on the LPCR[STPMD] bit settings.”