MCF5235 Reference Manual Errata, Rev. 2.2
Errata for Revision 2
Freescale Semiconductor
4
Figure 14-9/Page 14-17
Change CLKIN to CLKOUT
Add overbars to TS, CS, and TA.
Section 14.4.4.1/Page 14-17 Remove all text and figures in this section starting with “Since bus timings...”
Figure 15-3/Page 15-4
Figure incorrectly shows that EPDDR is 16-bits wide. Change to an 8-bit register with each
EPDDn bit a one-bit field from bits 7–1 to match Table 15-4.
Figure 16-2/Page 16-5
Re-labeled the WS states in the timing diagram. The first should be IWS to indicate that the
length of this wait state is determined by CSCR[IWS]. The rest of the wait states should be
IWS/SWWS to indicate that either CSCR[IWS] or CSCR[SWWS] determine the length of
the wait state depending on the value of CSCR[AA].
Figure 16-3/Page 16-5
Re-labeled the WS states in the timing diagram. The first should be IWS to indicate that the
length of this wait state is determined by CSCR[IWS]. The rest of the wait states should be
IWS/SRWS to indicate that either CSCR[IWS] or CSCR[SRWS] determine the length of the
wait state depending on the value of CSCR[AA].
Change Write labels on the data signals to Read.
Table 18-5/Page 18-8
Add the following note to the DACRn[CBM] field description:
Note: It is important to set CBM according to the location of the command bit.
Table 19-1/Page 19-5
Correct MIB block counters end address to 0x12FF.
Table 19-3/Page 19-8
Add RMON_R_DROP with an IPSBAR Offset of 0x1280 and a description of ‘Count of
frames not counted correctly’.
Section 19.3.6/Page 19-38 Add the following subsection entitled “Duplicate Frame Transmission”:
The FEC fetches transmit buffer descriptors (TxBDs) and the corresponding transmit data
continuously until the transmit FIFO is full. It does not determine whether the TxBD to be
fetched is already being processed internally (as a result of a wrap). As the FEC nears the
end of the transmission of one frame, it begins to DMA the data for the next frame. In order
to remain one BD ahead of the DMA, it also fetches the TxBD for the next frame. It is
possible that the FEC will fetch from memory a BD that has already been processed but not
yet written back (that is, it is read a second time with the R bit still set). In this case, the data
is fetched and transmitted again.
Using at least three TxBDs fixes this problem for large frames, but not for small frames. To
ensure correct operation for either large or small frames, one of the following must be true:
• The FEC software driver ensures that there is always at least one TxBD with the ready
bit cleared.
• Every frame uses more than one TxBD and every TxBD but the last is written back
immediately after the data is fetched.
• The FEC software driver ensures a minimum frame size,
n
. The minimum number of
TxBDs is then (Tx FIFO Size
÷
(n + 4)) rounded up to the nearest integer (though the
result cannot be less than three). The default Tx FIFO size is 192 bytes; this size is
programmable.
Figure 30-8/Page 30-7
Move SKMR[CTRM,DKP] bit fieldsfrom 11–7 to 12–8.
Table 30-2/Page 30-8
Correct bit locations for CTRM and DKP fields:
31–13 Reserved
12–9
CTRM
8
DKP
7–5
Reserved
Table 32-13/Page 32-13
Add the following note to the PBR[Address] field description:
Note: PBR[0] should always be loaded with a 0.
Table 1. MCF5235RM Rev 2 Errata (continued)
Location
Description