MCF5235 Reference Manual Errata, Rev. 2.2
Errata for Revision 2
Freescale Semiconductor
2
1
Errata for Revision 2
Table 1. MCF5235RM Rev 2 Errata
Location
Description
Figure 1-1/Page 1-3
Change instance of CIM to “CCM and Reset Controller”.
Section 1.3.1/Page 1-8
Change “Chip Integration Module (CIM)” to “Chip Configuration Module (CCM)”.
Move Reset sub-bullet (and its sub-bullets) up one level.
Table 2-1/Page 2-5
Change SD_CKE pin location from 139 to “—” for the 160QFP device.
Table 2-1/Page 2-6
Change QSPI_CS1 pin location from “—” to 139 for the 160QFP device.
Table 3-1/Page 3-4
Remove last sentence in C bit field description.
Table 3-5/Page 3-8
Change PC’s Written with MOVEC entry to “No”.
Section 3.4/Page 3-9
Change last bullet to “Use of separate system stack pointers for user and supervisor
modes”
Section 3.5/Page 3-10
Change last sentence in fourth paragraph (step 2) to “The IACK cycle is mapped to special
locations within the interrupt controller's address space with the interrupt level encoded in
the address."
Figure 4-9/Page 4-14
Add minus sign to the exponent so that it is “–(i + 1 – N)”.
Table 5-3/Page 5-7
Change reset value of ACR0, ACR1 to “See Section” since some of the bits are undefined
after reset.
Figure 5-2/Page 5-7
Change CACR fields to R/W, since they may be read via the debug module.
Table 5-5/Page 5-10
For split instruction/data cache entry, swap text in parantheses in the description field.
Instruction cache uses the upper half of the arrays, while data cache uses the lower half.
Figure 5-3/Page 5-11
Change reset value of ACR: Bits 31-16, 14-13, 6-5, and 2 are undefined, and other bits are
cleared.
Change ACR fields to R/W, since they may be read via the debug module.
Section 5.2.1.2/Page 5-11
Change note to:
NOTE
Peripheral (IPSBAR) space should not be cached. The
combination of the CACR defaults and the two ACRn
registers must define the non-cacheable attribute for
this address space.
Figure 6-1/Page 6-2
Change RAMBAR fields to R/W, since they may be read via the debug module.
Section 11.2.1.1/Page 11-3 After the first paragraph add the following note:
NOTE
Accessing reserved IPSBAR memory space could
result in an unterminated bus cycle that causes the
core to hang. Only a hard reset will allow the core to
recover from this state. Therefore, all bus accesses to
IPSBAR space should fall within a module's memory
map space.
Table 12-1/Page 12-5
Change SD_CKE pin location from 139 to “—” for the 160QFP device.
Table 12-1/Page 12-7
Change QSPI_CS1 pin location from “—” to 139 for the 160QFP device.
Table 12-9/Page 12-21
Change footnote from “...of the RCSC field in the CIM reset configuration register.” to “... of
the RCR[RCSC] field in the reset controller.”